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ADRF6612 Lock Detect value when ext LO is used

Category: Hardware

What will be the value of the Lock Detect output signal when the ADRF6612 is used with an external LO signal?

  • Hi Kevin,

    Thanks for the question. In the case external LO is used, the PLL lock signal will be irrelevant. So, it can be low as well.

    If the PLL is used, the lock detect signal should be high. We have not encountered any such case. If you have such issue, could you give answers to the following questions?

    1) Are you using the evaluation board? It has a LED (DS1) which turns on when PLL is locked.

    2) Is your output frequency correct when PLL is locked and lock detect signal is low? If the output frequency is near to the desired frequency, it means that the PLL is not locked.



  • Hello,

    new test results: 

    The eval board is not in use here. 

    When the loop is locked the carrier is stable with low phase noise and VCOVTUNE from the loop filter into pin 2 is about 1.5 volts which is in the middle of its range.  Under these conditions the Lock det signal is about 0.06V.  I can force the loop out of lock by grounding VCOVTUNE into pin 2, or, flipping the PFD polarity bit (B13 in 0x21).  In either case  the lock det signal goes high to about 3.2 volts, the carrier shifts significantly off frequency and becomes so unstable as to prevent a phase noise measurement of it. 

    Note negative PFD polarity is used when the carrier is locked and lock det is sitting low. Does the selection of the PFD polarity affect the polarity of the lock detect signal?

    Also please clarify. In the datasheet, in the description of the PFD_CTRL1 reg (0x21), it specifies 2 bits for REF_MUX_SEL however the choices show 3 bits are required.




  • Hi Kevin,

    Thanks for the update.

    1.5 V VCOVTUNE indicates the PLL is indeed locked. Is the desired LO frequency observed? If it is,

    Please try to obtain different outputs from the REF_MUX_SEL (for example REFCLK/2). If these are cannot be observed, this could point out the MUXOUT pin soldering issue, thus the lock detect signal seems low from that pin. If other parameters are correctly observed but not the REF_MUX_SEL, please let us know.

    PFD polarity does not effect the lock detect signal, it should be high if the PLL is locked.

    For the REF_MUX_SEL size, thank you for noticing this. Please try using bits [15:13] on Reg0x21 for controls. We will update this in the datasheet.



  • No new results yet with the REF_MUX_SEL. Going to the datasheet, we see this text which is somewhat ambiguous:

    "To ensure that the PLL locks to the desired frequency, follow the proper write sequence of the PLL registers. The PLL registers must be configured accordingly to achieve the desired frequency, and the last writes must be to Register 0x02 (INT_DIV in Table 25),

    Register 0x03 (FRAC_DIV in Table 25), or Register 0x04 (MOD_DIV in Table 25). When one of these registers is programmed, an internal VCO calibration is initiated, which is the last step in locking the PLL"

    We need to program all three registers 0x02, 0x03, 0x04 so can you advise on the order of writing all the registers? 

  • Hi Kevin,

    You can start writing register following Table 25 during initialization. Use the reset values for registers shown, and follow from top the bottom.

    For the PLL cycle, writing register 0x02, following by 0x03 and 0x04 should work, but also please check the required register setting (eg. internal LO, VCO selection) mentioned in the "Circuit Description" section on the datasheet.



  • Hi Gokhan, 

    new results: the MUXOUT pin produces correct results with other settings of the the REF_MUX_SEL reg, however, the MUOUT signal is still inverted when REF_MUX_SEL is set to LOCK_DET. 

    Can you tell me which supply domain is used for the REF_MUX_SEL circuitry?

    Another question: in the 6612 datasheet, supply pins VCC1, VCC2, VCC7 and VCC12 are 3.55V - 3.85V, nominal 3.7V supply pins. However in the eval board user guide, these pins are tied to VCC_SYNTH and the guide instructs that this signal should be tied to 5V. Can you clarify?

    thanks! KevinL

  • Hi Kevin,

    Sorry for the delayed answer.

    From what you have described, the PLL is locked and you can read REF_MUX_SEL correctly. According to the datasheet, you should see logic high for the LOCK_DET for this application.

    For the REF_MUX_SEL, VOL is between 0V and 0.25V, and VOH is between 2.7V and 3.3V.

    We are working on understanding why you see logic low for LOCK_DET, and why there are two different values for pin supply voltages, and we will get back to you.



  • Hi Kevin

    If you can share, we can also investigate your schematic to see if there is something problematic and causing that you are obtaining a low LOCK_DET signal.



  • Hi Gokhan,

    the design is utilizing the high efficiency mode and running all supply voltages at 3.7V. Here are msmts from other pins:

    LDO1-4: all measure very close to values listed in table 10 of the datasheet.

    DECL’s 1,2,3 measure 2.8V,  DECL4 = 0V, DECL 5=2.5V.

    Also I mis-reported the REF_MUX_SEL operation. Here is the latest: When using the other settings of the REF_MUX_SEL bits (reg 0x21, bits 15-13), only the ref clk appeared when selected with code code 010.  Refclk/2 and all other codes were steady DC voltage about 1.8V except for Lockdet.  As we discussed, Lockdet is inverted. 

    I will collect a schematic and send to you.

    thanks! Kevin L. 

  • Hi Kevin

    Thanks for the update. We will be working on the schematic once we receive it. At the same time, we are working on why you obtain such behavior from the LOCK_DET pin.

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