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when ADF5356 relock ... phase synchronization ?

Hi Frank,
   What I need is After the PLL is powered on again, each locking phase is consistent with the reference signal,I saw in the application manual that you mentioned that the phase synchronization can be maintained after software restart,Now I do the following steps:
    First, a reference signal of 10 MHz is input and a reference signal of 2482 MHz is output.
    The second step is to let the PLL enter the off mode (the manual says that the internal value of the register will not change at this time).
    The third step is to write the value of register 3 and only change the power off mode. At this time, it cannot be locked.
I've tried many times recently, but I haven't succeeded. What steps are missing? Can you give me some examples?
For example, the step of phase-locked loop phase re locking or control word.
In addition, can the phase-locked loop be synchronized with the reference signal or the phase relationship be consistent after power on again?
   thank you