I have a design , the ref clock and PFD is 12.5Mhz input, i need PLL output is 100Mhz, and the output 100Mhz
must has the same phase relationship with the ref clock(12.5Mhz) every time when power up, so i select ADF4372
and use vco divider feedback paht to the PFD, the VCO = 6.4Ghz, and output divider = 64, the N counter = 8, the
PLL can not lock and output is about 140Mhz, if I use fundamental feedback paht to N counter, the PLL can lock and
work well. then i find the N counter must be least 16 when inter mode and prescaler 4/5(all the test use this setting) in
datasheet page 4, and must be 20 to 32767 in datasheet 18. so i change the setting , set R counter =4 and PFD = 3.125Mhz
then the N counter = 32( more than 16 or 20) ,but the PLL still can not lock and output correct frequency .
who can help me to resolve this problem? how can i use the ADF4372 in divider feedback path mode ?
