I am currently trying to design a single frequency reference at 14.65GHz. I am using the ADIsimPLL software and got to a design, but there seems to be an issue I wanted to ask about. The design was intended for a HMC531 VCO with the divide by 4 (3.6625 GHz) output being fed back into the PLL chip. The software predicted the VCO requires a tuning voltage of ~8.2V so I choose the ADF4150HV to avoid needing an amplifier between the PLL chip and the VCO. However, when i was looking at the datasheet for the ADF4150HV (pictured below) the maximum RFin frequency is shown to be 3 GHz. The design ADIsimPLL produced was for a divide by 4 output of 3.6625GHz. When I looked at the datasheet for the ADF4150 it's max RFin is 4 GHz, capable of handing the divided by four output.
Am I missing something important? Is the ADIsimPLL software wrong? Is the datasheet wrong? Any further insight into this would be much appreciated. Thanks.
Bonus question: In the ADF4150 does the max RFin frequency vary depending on input RF power? For example, with the output buffers disabled, as long as the input power is greater than -5 dBm the chip will operate up to 5 GHz? However, if the power drifts below -5 dBm the max inptut frequency will drop to 4 GHz?