ADF4371 Phase Noise

Hi, could you please try to attach ADIsimPLL file again? Sometimes on EZ you need to compress (zip) the .pll file before it can be attached. In general for improving phase noise it is best to use the highest PFD frequency possible. Is there any particular offset you are trying to get an improvement at, what are your PN targets at each offset?

What's the step size i.e. is this an integer N use case? FOM improves when in integer N operation and SDM is disabled. We also have a new PLL that will be releasing mid April which has a ~12GHz fundamental VCO and has better FOM than ADF4371. It's integer N only though, in any case the part number will be ADF4377.

Hi, could you please try to attach ADIsimPLL file again? Sometimes on EZ you need to compress (zip) the .pll file before it can be attached. In general for improving phase noise it is best to use the highest PFD frequency possible. Is there any particular offset you are trying to get an improvement at, what are your PN targets at each offset?

What's the step size i.e. is this an integer N use case? FOM improves when in integer N operation and SDM is disabled. We also have a new PLL that will be releasing mid April which has a ~12GHz fundamental VCO and has better FOM than ADF4371. It's integer N only though, in any case the part number will be ADF4377.

In the file, I like to specify the reference oscillator (100MHz by Crystek) as used in the ADF4371  EVB. How do I specify this?  Currently, it is specified as custom, but I am not what has been specified in terms of the phase noise of the reference oscillator by the software.

Step size  is not critical as I want to good phase for the mixer and it is not required to hop.  The Mixer have x2 or x4 which would degrade phase noise.

The PLL is required to change LO frequency in steps of 200kHz if the IF frequency changes to give a fixed RF output. 

Just to clarify, low phase noise is required which I guess fine frequency step is required and keeping high Pfd. Will the fine frequency step allow the LO to step the frequency in steps of 200kHz.  I look forward to hearing from you regarding ways to improve phase noise. 

Hi, okay sounds like you will probably need fractional-N operation. You should be using the ref doubler to get 200MHz PFD frequency for best PN performance.

Here is a forum post which describes how to model the reference component's phase noise in ADIsimPLL.
RE: ADF5610 - Wenzel 100MHz ref specs

Hi

Is it possible to use 260MHz pfd?

What fractional-N would you recommend for 200MHz? A revised pll file would be much appreciated 

I tried to change the pfd to 200MHz but the software states that max pfd is 160MHz. I thought the highest is 260MHz. Why does the software not allow to use higher pfd?

My mistake, ADF4371 max PFD frequency is limited to 160MHz in fractional N mode. PFD freq can go up to 250MHz in int mode

Hello

Thank you for confirming.  Is there a way to improve phase noise even more using higher pfd in integer-n mode for my application?

I modified the file I attached in using 5610 in the simulation.  It gave slightly better phase noise at some offsets 100kHz loop BW.

I am confused why 5610 is slightly better as FOM is worse than 4371. Could you please explain why?

Hi, ADF5610 has a lower phase noise floor VCO so it may be better than the ADF4371 at the higher frequency offsets/lower noise floor. ADF4371 PLL has better FOM so its in band phase noise will be superior

Hello

Thank you. Far out noise is important as signal's BW are in tenss if MHz.

I was wondering if there is any improvement in integrated phase noise (KHZ to 40MHz and far out VCO phase noise in using the ADF41513 with external VCO. Whaat external VCO is recommended for 11-11.5GHz?

Are there PLL Chips with integrated VCO available with fundamental VCO frequency covering 11 to 12GHz band?