Post Go back to editing

ADL5519 POWER-DOWN INTERFACE

Hello,

We use the ADL5519 in VWSR mode.

We adjust ADJA & ADJB with VREF signal to optimize the temperature performance by a resistor voltage divider.

We need to powerdown the ADL5519.

To powerdown the component, ADJA, ADJB and PWDN pins need to tied to Vcc.

How to manage the powerdown function and the Temperature Compensation Interface on ADJA & ADJB pins ?

thanks

Parents
  • Hi there, 

    One way would be to use analog switches or JFET switches on ADJA and ADJB inputs. The ADJA and B inputs get switched to power supply voltage to disable, or to the resistive dividers off VREF to enable. That would work, it's just not a very elegant solution. And PWDN would also need the appropriate logic level drive. 

    Another solution would be to not use VREF for the ADJA, ADJB resistive dividers. Instead use voltage dividers off of a well regulated power supply to the IC. At each voltage divider leg to ground, put an NPN collector-emitter junction in series. Then drive both transistors together. This way, when transistors are in cutoff, the ADJA and ADJB inputs pull high by the series leg of the voltage dividers. When the transistors are driven in saturation, the ADJA and ADJB voltages are determined by the voltage divider formula based on regulated input voltage to the divider. And like the prior solution, PWDN would also need the appropriate logic level drive.

    Of the two approaches mentioned above, the latter would be fairly easy and cost-efficient to implement.

    Kindly advise if the description is not clear, and I could sketch out a schematic to try.  -Bruce H. 

Reply
  • Hi there, 

    One way would be to use analog switches or JFET switches on ADJA and ADJB inputs. The ADJA and B inputs get switched to power supply voltage to disable, or to the resistive dividers off VREF to enable. That would work, it's just not a very elegant solution. And PWDN would also need the appropriate logic level drive. 

    Another solution would be to not use VREF for the ADJA, ADJB resistive dividers. Instead use voltage dividers off of a well regulated power supply to the IC. At each voltage divider leg to ground, put an NPN collector-emitter junction in series. Then drive both transistors together. This way, when transistors are in cutoff, the ADJA and ADJB inputs pull high by the series leg of the voltage dividers. When the transistors are driven in saturation, the ADJA and ADJB voltages are determined by the voltage divider formula based on regulated input voltage to the divider. And like the prior solution, PWDN would also need the appropriate logic level drive.

    Of the two approaches mentioned above, the latter would be fairly easy and cost-efficient to implement.

    Kindly advise if the description is not clear, and I could sketch out a schematic to try.  -Bruce H. 

Children
No Data