HMC8191 DC FEED FOR IF1/2 ?

Hi all,

We've checked the thread linked below, and they're asking questions similar to ours, but they're still unanswered.

Can anyone give us some good advice?

HMC6505A LO nulling 

ez.analog.com/.../hmc6505a-lo-nulling

Best regards,

sss

Can anyone give us some good advice?

This question is the basic information needed for a customer's circuit design.
We think this design information should be added to the datasheet.

1. Input DC voltage range specififation for IF1,2 ?

We know the following:
However, we do not know how to control the voltage range to limit the current.

Ensure that the source or sink current used for LO suppression is <3 mA for each IF port to
prevent damage to the device.

The common-mode voltage for each IF port is 0 V.

2.Please provide a specific, recommended circuit or ADI test circuit for DC feed to IF1 and IF2.

Best regards,

sss

Can anyone give us some good advice?

Hi, The usual applications engineer for this device has recently left ADI. I will try to find the person taking over responsibilities and direct them to this question. Thanks for your patience

Hi SSS, 

On the datasheet of the HMC8191 page 4 in table 2 (Absolute Maximum Ratings) table we list a maximum source/sink current of 3mA. That means the total current to by synced or sourced on the IF1/IF2 pins cannot exceed that current. For LO nulling the voltages on either IF1 or IF2 do not have to match such that you will get some current draw. Typically we have found that the voltages needed to null the LO are on the order of -0.1 to 0.1V requiring a fine voltage step of 0.001V based on how deep of a null you are desiring. 

Typically for adjusting the DC voltage on each IFX port, we would do the following(At each step below monitor the LO leakage to ensure  level is reducing):

1. Adjust IF1 from 0V to 0.1V in at least 0.01V steps, stop adjusting if the LO leakage starts to get worse from the previous voltage. 

2. If the above positive step resulted in no improvement, adjust IF1 from 0V to -0.1V in at least 0.01V steps, stop adjusting if the LO leakage starts to get worse from the previous voltage.

3.  Adjust IF2 from 0V to 0.1V in at least 0.01V steps, stop adjusting if the LO leakage starts to get worse from the previous voltage. 

4. If the above positive step resulted in no improvement, adjust IF1 from 0V to -0.1V in at least 0.01V steps, stop adjusting if the LO leakage starts to get worse from the previous voltage.

At this point if the desired LO leakage is still not met I would loop back to step 1 and run through the steps again, but do not go back to 0V on the DC voltage, but start adjusting +/- in 0.1V steps from the voltages found in the first round of adjustments to fine tune the offsets. 

Thank you for this response. Very helpful.

On my HMC8191 evaluation board, I see that on the two IF channels, the DC bias required to minimize the LO leakage are approximately -30mV and +10mV.

But I have not tested this across multiple evaluation boards to see whether these DC bias voltages are consistent across different chips.