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ADF4159 Phase noise improvement

Hi team,

I integrated the ADF4159 PLL evaluation board with an external VCO i.e., HMC510LP5E to generate desired frequencies for the application I'm working on. Also I'm giving the reference signal of 100MHz from an external clock source(LN100) instead of on board OCXO. I'm trying to generate a ramp signal that covers a range of 30MHz, starting from 9300 MHz to 9330MHz. I designed the loop filter by setting the PFD to 25MHz using the ADIsimPLL software. 

Now, I have few questions as follows

  1. Can the phase noise produced in ADF PLL during CW and FMCW frequencies generation be same in both cases?
  2. How do I estimate the exact phase noise in PLL I'm using?
  3. How can I improve the phase noise? Is it dependent on the loop filter design or PFD frequency setting?
  4. Does using an external VCO and OCXO affect the phase noise produced in PLL?

I'm attaching the loop design file screenshot here in case anyone wants to know the settings I set.

Thanks in advance.

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  • Hi,

    The phase noise at low freq offsets is normally dominated by the PN of the reference signal. At far out offsets, the VCO PN component is dominant. At the mid offsets the PLL's figure of merit (FOM) is most important. The FOM essentially the noise floor of the PLL. PLL in-band noise is a function of the PFD frequency and the N counter value used. The FOM of the PLL will be slightly worse in fractional N mode due to sigma delta modulator operation (you need the SDM for ramping operations). The components of the FOM are 20log(n) and 10log(PFD freq). So you can see if is better to keep N value as small as possible since it's the larger contributor, and this is done by increasing the PFD frequency. In other words, it is best to keep the PFD freq as high as possible. 
    You can often improve phase noise by optimising the loop filter BW to help filter some noise based on if your reference, VCO or PLL has the best noise performance. For example, for an reference clean up circuit where the reference has poor PN you can set LBW very low to compensate for this and ride the performance of the VCO and PLL. You can see the predicted phase noise based on these components in the phase noise plot in the freq domain tab of ADIsimPLL. A simple experiment is to increase/decrease the LBW in the loop filter section using pg up/pg down keyboard keys and look how the PN response changes.

    One thing to note is that a narrow LBW will increase PLL lock time. Since you are using ADF4159 in a ramping application, the PLL lock time is an important aspect. Note ADIsimPLL will also simulate the ramp linearity (see here), so you can check that ramp looks okay based on the loop filter design you have chosen to meet your phase noise targets.

    External vs integrated VCO can effect a PLL's FOM but in general the spurs when using an integrated PLLVCO are the bigger concern.

    I have attached an example design for ADF4159 and HMC510 which might help get you started.ADF4159_HMC510_example.zip

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