I integrated the ADF4159 PLL evaluation board with an external VCO i.e., HMC510LP5E to generate desired frequencies for the application I'm working on. Also I'm giving the reference signal of 100MHz from an external clock source(LN100) instead of on board OCXO. I'm trying to generate a ramp signal that covers a range of 30MHz, starting from 9300 MHz to 9330MHz. I designed the loop filter by setting the PFD to 25MHz using the ADIsimPLL software.
Now, I have few questions as follows
- Can the phase noise produced in ADF PLL during CW and FMCW frequencies generation be same in both cases?
- How do I estimate the exact phase noise in PLL I'm using?
- How can I improve the phase noise? Is it dependent on the loop filter design or PFD frequency setting?
- Does using an external VCO and OCXO affect the phase noise produced in PLL?
I'm attaching the loop design file screenshot here in case anyone wants to know the settings I set.
Thanks in advance.