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HMC1082LP4E Gate Resistance/Capacitance

Thread Summary

The user inquires about the gate current vs voltage bias relationship and the necessity of external gate resistance for the HMC1082LP4E to ensure fast bias times. The gate is high impedance (meg ohms) and typically draws 100-200 μA at Psat, so external bias resistance is not required. For stability, the 2.2 μF capacitors on the gate and drain can be removed, and C5, C6, C7 should be increased to 10,000 pF. The user plans to ramp the gate voltage rapidly (within 1 ms) using a DAC, and the primary timing limitation is the gate-channel capacitance, though specific capacitance values are not available.
AI Generated Content

The HMC1082LP4E datasheet pin description on page 8 illustrates a resistance in series between the device gate and the Vgg bias pin on the package.  Does this resistance model the device gate current vs voltage bias relationship?  Do you recommend any external gate resistance to help limit the gate current, or does the device gate impedance generally provide sufficient current limiting?  I would like to minimize any additional gate capacitance (and any resistance if needed) at the device to ensure fast bias times (1 to 2 ms) and reduce the PCB BOM.  Thank you for your assistance!  

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