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HMC1082LP4E Gate Resistance/Capacitance

		
	
				

			

									
					    jpeter192
					
							

            
            			
				
									
											
			
			
				
			
			
			    	
			                    
                
				                on Feb 23, 2022 
				
			
			
		

		
		                    	    

        	    
Thread Summary

                The user inquires about the gate current vs voltage bias relationship and the necessity of external gate resistance for the HMC1082LP4E to ensure fast bias times. The gate is high impedance (meg ohms) and typically draws 100-200 μA at Psat, so external bias resistance is not required. For stability, the 2.2 μF capacitors on the gate and drain can be removed, and C5, C6, C7 should be increased to 10,000 pF. The user plans to ramp the gate voltage rapidly (within 1 ms) using a DAC, and the primary timing limitation is the gate-channel capacitance, though specific capacitance values are not available.
                        	    

                
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The HMC1082LP4E datasheet pin description on page 8 illustrates a resistance in series between the device gate and the Vgg bias pin on the package.  Does this resistance model the device gate current vs voltage bias relationship?  Do you recommend any external gate resistance to help limit the gate current, or does the device gate impedance generally provide sufficient current limiting?  I would like to minimize any additional gate capacitance (and any resistance if needed) at the device to ensure fast bias times (1 to 2 ms) and reduce the PCB BOM.  Thank you for your assistance!  

			

			
									
		                             
                        

    

                                            
                 rf & microwave
                
                                                    
                 hmc1082lp4e
                
                                
            

    
    
		


				
				        
        		

			
						
									
												
			
			
                        
                                    
                        
                                                    
                        
            
			            
						
						
			
			
			
			
		


        
        
        
    
					

			





















	

	

					



			


				
	









	
    
	

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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Mar 1, 2022 1:31 PM
            
            
						
			            		
    
		
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    Hi ipeter192,
    

                        The gate is a high impedance, meg ohms. The gate current is going to be on the order of 100 - 200 micro amps at Psat. The gate does not require external bias resistance. The gate voltage range is -2V to 0V. The gate voltage is adjusted to achieve a 220 mA drain current. 
    

    You might be able to remove the 2.2uF caps from the gate and drain. You would need to check and make sure the HMC1082 is stable in your application. If you do remove the 2.2 uF capacitors, I suggest changing C5, C6, C7, from 1000pF to 10,000 pF. I have done some experiments using the EVB and find the 1000 pF caps are not quite enough to keep the part stable under all conditions. 
    

    Are intending tp operate The HMC1082 in pulse mode, ( pulsing either the drain or gate) or, just need the part to fully bias when you apply the dc voltages?
    

    Regards,
    

    Jim B
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
				
						
				
				
				
		
		
    
			
		
    
	
    

    

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                on Mar 2, 2022 7:54 PM
            
            
												
						in reply to ADIApproved
					
										
			            		
    
		
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    Thank you for the reply Jim.  I was planning on ramping the gate voltage rapidly from pinch-off to nominal bias as quickly as possible (within 1 ms or so) using a DAC for bias control.  If 10 nF external capacitance is all that is required, then RC time constant from the PCB trace and this capacitance should be quite low.  I would expect the primary timing limitation is set by the gate-channel capacitance as it establishes bias at 220mA.  Do you happen to have any data (or estimates) for this gate-channel bias delay?  (or estimated capacitance).  Thanks again for your assistance!
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
				
				
				
		
		
    
			
		
    
	
    

    

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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Mar 3, 2022 12:48 PM
            
            
												
						in reply to jpeter192
					
										
			            		
    
		
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    Hi jpeter192,
    

                          I do not have an for the gate/channel delay or estimated capacitance.
    

    Regards,
    

    Jim B
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
				
				
				
		
		
    
			
		
    
	
    

    

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