I am trying to use the Phase adjust feature with the ADF4351 in Integer mode.
First of all, the behaviour of the hardware setup is checked without phase adjustement. The board in use is the ADF4351 evalboard, with 10MHz external reference. PFD frequency is set to 25kHz. Loop filter bandwidth is calculated for RBW=2.5kHz and phase margin 48°. The expected output signal frequency is 45MHz (divided feedback).
In these conditions, the lock detect signal is high, and the output RF signal shows good phase noise characteristics.
After that, I have tried to enable the phase adjust feature:
- Enable SD EN with FRAC = 0 (hidden test modes menu)
- Enable Phase adjust
As long as the "SD EN with FRAC=0" is set, the output signal is degradated : Lock detect low, phase noise quite bad.
I have tried several values in REG1, in order to change the phase step value. I have the feeling that the smaller the phase step is, the higher the degradation is. Depending of the current phase, the PLL output can be clearly unlock (signal observed at oscilloscope).
Everything return to a normal behaviour when I disable the "SD EN with FRAC = 0" setting.
I do not understand what I am doing wrong.
Thanks for your help