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Synchronization of two ADF4159 PLL

Hi Team,
We are using two ADF4159  in our application. We have the following queries.
  1. How to synchronize two ADF4159 PLL's such that both should generate ramp signals at same time?
  2. Is there any trigger pin on ADF4159 chip such that upon providing logic high from a MCU to PLL, the PLL should generate FMCW signal?
Kindly share any information or documents regarding the same.
  • The ADF4159 has a TxData pin, a pulse on this pin will start a ramp. Please consult the datasheet, in the register description section - search for "TxData".

    You can supply both ADF4159s with a TxData pulse at the same time to start them ramping at the same time. Depending on how tight your timing requirements are, you may want to share the same reference signal between both ADF4159 chips and synchronise the TxData pulses with this reference signal (perhaps using a flip-flop). This would mean the TxData edge arrives at both PLLs on the same reference edge and therefore the ramp on both should start at precisely the same internal count.