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ADMV4420 Programming sequence

Hi,

The data sheet of the ADMV4420 states that the N dividers (INT, FRACT,MOD) are all double buffered and the actual registers are loaded when the register INT_L (address 200H) has been written: this to prevent any unwanted intermediate registers configuration be activated. Now I do not understand why, at page 40 of the data sheet, is indicated a "recommended programming sequence": is there any additional "hidden" requirement to be followed? In addition, what does it mean "Program 16 SPI clock cycles", at the end of the sequence: it is just a delay to let the VCO Auto-calibration execute, or it is required to complete the sequence itself? And if the latter applies, what about the SDO and CS lines ?

Thanks.

Maurizio

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