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HMC832 : Frequency tolerance corresponding to lock detect signal

I wanted to know:

1. What is the frequency tolerance figure when lock detect signal goes high (upon tuning the PLL to a new frequency)? That is, within how offset has frequency settled, at the instant lock detect is driven high?

2. How the lock detect register configuration change the frequency tolerance value, if it does?

Thank you.

  • Hi,

    The frequency should be highly accurate where the divided VCO edge and divided reference edge stay in the same window for a number of cycles defined in register 0x07[2:0] (2048 cycles by default). However the phase of the output signal may drift back and forth or drift in one direction a little while the phase is getting stable. 

    If the number of cycles (0x07[2:0]) is increased, indicating lock detect takes more time so the accuracy should increase for both frequency and phase. 

    Another setting that affects the lock detect indication is the Digital Lock Detect Window size. It will be more difficult to indicate a lock detect if the window size is decreased. However this may even cause the lock detect mechanism to failure, specifically at temperature edges. The window size should be tuned very carefully.