Ultra low frequency of REF PLL Select

Question

When I am doing an experiment, I analyze a 100Hz signal and want to use a hardware phase-locked loop for frequency stabilization or output a stable multiplier (1M), is there such a phase-locked loop?

aandrews · Accepted Answer

Some of our HMC PLLs (e.g. HMC704) have "DC" listed as the minimum reference frequency. This is mainly theoretical since the rise/fall time a 100Hz signal would require for the PLL to function would need be exceptionally fast. I am not sure it is feasible to to achieve the required slew rate in practice without exceeding the absolute max ratings of the PLL. In reality the min reference freq is more like 200kHz or so. The reference signal also needs to be AC coupled, at 100Hz this is going to be problematic. 
 So I do not think a traditional PLL will work. What about taking a look at our TimerBlox devices? 
 https://www.analog.com/en/parametricsearch/11410#/

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Ultra low frequency of REF PLL Select

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