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HMC1197 SPI SEN

Can you clarify the behavior of the SPI interface regarding the state of the SEN pin?

Datasheet section 1.8.1 says:

g. Master asserts SEN after the 32nd rising edge of SCLK.

h. Slave registers the SDI data on the rising edge of SEN.

i. Master clears SEN to complete the WRITE cycle.

This implies that the SEN pin is unlike the chip-select in standard SPI. Can the SEN pin be asserted (pulled low) before the host finishes writing a packet? Does the HMC1197 register data on the SDI pin if the SEN pin is de-asserted (high)?

I am not able to communicate with the HMC1197. I believe it's because the MCP2210 USB-SPI converter I'm using has a quirky behavior where it generates a spurious SCK pulse before pulling the chip-select (SEN) pin low to write a packet. For most devices this doesn't matter because SPI data isn't accepted until chip-select is low. It seems it may create a malformed packet with the HMC1197.

Thanks

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  • Hi jfed,

    SEN can work like chip-select or SPI enable. you can set SEN low such as the common SPI communications but the rising edge of SEN would latch the previous 32 bits data.

     

    - Can the SEN pin be asserted (pulled low) before the host finishes writing a packet?

    Please clarify what means "before the host finishes writing a packet?" 

    - Does the HMC1197 register data on the SDI pin if the SEN pin is de-asserted (high)?

    When SEN pin is set high, the previous 32-cycle data is latched.

    Thanks,

    Nao

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  • Hi jfed,

    SEN can work like chip-select or SPI enable. you can set SEN low such as the common SPI communications but the rising edge of SEN would latch the previous 32 bits data.

     

    - Can the SEN pin be asserted (pulled low) before the host finishes writing a packet?

    Please clarify what means "before the host finishes writing a packet?" 

    - Does the HMC1197 register data on the SDI pin if the SEN pin is de-asserted (high)?

    When SEN pin is set high, the previous 32-cycle data is latched.

    Thanks,

    Nao

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