i'm just trying to figure out how i can get the ADF5902 to work. I have the exact same problems with the PLL as described in this post.
I'm also a student at the RWTH Aachen and writing my thesis on designing a radar shield for an Arduino. For this purpose i will use the ADF5902 in combination with the ADF5904. Niklas R, from the post above, was my predecessor and i thought i learned from his mistakes. But currently I am stuck with the same problem.
So this time, we wanted to be on the safe side and kept to the reference design. So i choose a 100MHz reference oscillator (DSC1001) and use the same loop filter design as on the evaluation board for the ADF5902. If I try to look a single frequency at 24.1GHz, using this initialization procedure:
0x02000007, // R7 | Master reset 0x0000002B, // R11 | Reset the counters 0x0000000B, // R11 | Enable counters 0x0018000D, // R13 | Enable ramp divider 0x1D32A64A, // R10 | Reserved 0x2A20B929, // R9 | VCO calibration setup 0x40003E88, // R8 | Set the VCO frequency calibration divider clock to 500 -> 100 kHz 0x800FE520, // R0 | Power up LO, ADC and VCO // delay 10us 0x01800827, // R7 | R = 1, double = 0, divider = 1, PFD = 50 MHz, CLK1 = 2048 => fPFD/CLK1 < 25kHz 0x00000006, // R6 | Set the LSB FRAC = 0 0x01E28005, // R5 | INT = 241, FRAC = 8388608, N = 241 0x00000004, // R4 | AnalogTestBus = None -> Set the ATEST pin to high impedance 0x01897803, // R3 | Sets the I/O level to 3.3 V, CAL_BUSY to MUXOUT 0x00020642, // R2 | ADC_CLK_DIV = 50, Set ADC clock to 1 MHz 0xFFF7FFE1, // R1 | Set the transmitter amplitude level to 8dBm 0x800FE720, // R0 | VCO_Cal = 1, Start the VCO frequency calibration // delay 1200us 0x800FE540, // R0 | Turn Tx1 on, Tx2 off, and LO off 0x800FED40, // R0 | Tx1 amplitude calibration // delay 500us 0x800FE540, // R0 | Turn Tx1 on, Tx2 off, and LO off 0x00000011, // R17 | Reserved 0x0000000D, // R13 | Clock divider off 0x004F000C, // R12 | Charge pump current = 2.24 mA 0x2800B929, // R9 | Normal Operation 0x0100A827, // R7 | R = 1, double = 0, divider = 1, PFD = 50 MHz, CLK1 = 10 0x00000006, // R6 | Set the LSB FRAC = 0 0x01E20005, // R5 | PFD = 50 MHz, INT =241, MSB FRAC = 0; lock to 24.1 GHz 0x0189F803; // R3 | Ramp Status tp Muxout, I/O voltage level to 3.3 V
In this example, I set the PFD frequency to 50MHz, but I also tried a PFD frequency of 10 0MHz.
With that procedure i can measure an output signal with a bandwidth of around 4MHz and a peak at 24.1GHz, which obviously indicates a not perfect locked PLL. In this case the charge pump current is set to 2.24mA. If i reduce the current to 0.28mA the bandwidth gets narrower, as you can see in the second image.
The voltages at the Rset and Vreg pin are also regulated well. If i look at the R_Divder, N_Divider or R_Divider/2, N_Divider/2 i can see the expected 50MHz signal, respectivly 25MHz signal.
and both the R_Divider/2 and N_Divider/2 look similar:
So, i tried a lot of things but i'm running out of ideas. Do you have any suggestion what i can try next?
Thanks in advance!