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ADF5902 PLL not locking

Hey, 

i'm just trying to figure out how i can get the ADF5902 to work. I have the exact same problems with the PLL as described in this post.

I'm also a student at the RWTH Aachen and writing my thesis on designing a radar shield for an Arduino. For this purpose i will use the ADF5902 in combination with the ADF5904. Niklas R, from the post above, was my predecessor and i thought i learned from his mistakes. But currently I am stuck with the same problem. 

So this time, we wanted to be on the safe side and kept to the reference design. So i choose a 100MHz reference oscillator (DSC1001) and use the same loop filter design as on the evaluation board for the ADF5902. If I try to look a single frequency at 24.1GHz, using this initialization procedure:

0x02000007, // R7   |    Master reset
0x0000002B, // R11  |    Reset the counters
0x0000000B, // R11  |    Enable counters
0x0018000D, // R13  |    Enable ramp divider
0x1D32A64A, // R10  |    Reserved 
0x2A20B929, // R9   |    VCO calibration setup
0x40003E88, // R8   |    Set the VCO frequency calibration divider clock to 500 -> 100 kHz
0x800FE520, // R0   |    Power up LO, ADC and VCO
// delay 10us
0x01800827, // R7   |    R = 1, double = 0, divider = 1, PFD = 50 MHz, CLK1 = 2048 => fPFD/CLK1 < 25kHz
0x00000006, // R6   |    Set the LSB FRAC = 0
0x01E28005, // R5   |    INT = 241, FRAC = 8388608, N = 241
0x00000004, // R4   |    AnalogTestBus = None -> Set the ATEST pin to high impedance
0x01897803, // R3   |    Sets the I/O level to 3.3 V, CAL_BUSY to MUXOUT
0x00020642, // R2   |    ADC_CLK_DIV = 50, Set ADC clock to 1 MHz
0xFFF7FFE1, // R1   |    Set the transmitter amplitude level to 8dBm
0x800FE720, // R0   |    VCO_Cal = 1, Start the VCO frequency calibration
// delay 1200us
0x800FE540, // R0   |    Turn Tx1 on, Tx2 off, and LO off
0x800FED40, // R0   |    Tx1 amplitude calibration
// delay 500us
0x800FE540, // R0   |    Turn Tx1 on, Tx2 off, and LO off
0x00000011, // R17  |    Reserved
0x0000000D, // R13  |    Clock divider off
0x004F000C, // R12  |    Charge pump current = 2.24 mA
0x2800B929, // R9   |    Normal Operation
0x0100A827, // R7   |    R = 1, double = 0, divider = 1, PFD = 50 MHz, CLK1 = 10
0x00000006, // R6   |    Set the LSB FRAC = 0
0x01E20005, // R5   |    PFD = 50 MHz, INT =241, MSB FRAC = 0; lock to 24.1 GHz
0x0189F803; // R3   |    Ramp Status tp Muxout, I/O voltage level to 3.3 V

In this example, I set the PFD frequency to 50MHz, but I also tried a PFD frequency of 10 0MHz. 

With that procedure i can measure an output signal with a bandwidth of around 4MHz and a peak at 24.1GHz, which obviously indicates a not perfect locked PLL. In this case the charge pump current  is set to 2.24mA. If i reduce the current to 0.28mA the bandwidth gets narrower, as you can see in the second image.

The voltages at the Rset and Vreg pin are also regulated well. If i look at the R_Divder, N_Divider or R_Divider/2, N_Divider/2 i can see the expected 50MHz signal,  respectivly 25MHz signal.

R_Divider:

N_Divider:

and both the R_Divider/2 and N_Divider/2 look similar:

So, i tried a lot of things but i'm running out of ideas. Do you have any suggestion what i can try next?

Thanks in advance!

Best regards, 

Philipp

Parents
  • Are you using the same board as Niklas or have you done your own re-spin?

    Regards,

    Alex

  • I have made a complete new design. As said, oriented to the reference design. 100MHz reference osciallator, same PLL loop design, the ADP7104 as power supply for the transmitter and the ADP150 for the oscillator. We put the decoupling capacitors as close as possible to the pins. This time, we really wanted to make sure the design would work.  

    I don't know, what we are doing wrong :/ Is it that complicated to make a working PCB design for this component?

  • That's great that the SPI write/readback is now working.

    Register 0:
    Bit DB31 is a special bit for writing to this register, as the address bits are all zeros. It must be set to 1 when writing, but it will read back 0.
    Bit DB20 can be set to 1 or 0 on ADF5902; it won't have any effect.

    Register 7:
    Bit DB24 is only set to zero during the master reset write (step 1 of the init sequence). For calibration and normal operation, it is set to 1 (steps 9 & 37).

    The master reset, VCO cal, Tx1 cal and Tx2 cal bits will all automatically reset to zero after their respective functions are executed.

    Those calibration times for the VCO and Tx1 amp are exactly what I would expect, so it looks like the calibrations have taken place. Has your output signal improved at all?

    I'm not familiar with Altium, but I can try to look at your design if you share it with me.

  • The output signal has unfortunately not improved. Also I think that the calibration worked before, since I did not expect the CAL_BUSY signal to be high only for that short time then I made a wrong measurement. So probably another measurement error I made before.

    Here is a link, were you can have a look on my design:

    AltiumViewer

  • Hi,

    Have you looked at the design yet?

  • Apologies for not replying sooner. I did look at the ADF5902 part of the design, and as far as I can tell everything is OK in terms of the schematic. I am not a PCB layout expert, but I think that looks fine too. I am running out of things to suggest.

    As I mentioned in an earlier post, I have verified on a customer evaluation board that the initialisation sequence that you attached to your first post locks the ADF5902 to 24.1 GHz with output on Tx1. I haven't tried your later sequences, but as far as I can tell there are only minor differences that should have no effect on whether the device locks or not.

    The calibration times you have observed on the MUXOUT pin seem correct, and the video you posted appears to show the VCO oscillating. The issue seems to be with the charge pump, but I don't know why it would not be working unless damaged somehow.

    I notice from your board that the Tx outputs are both connected to patch antennas. How are you measuring the output signal? With a horn antenna?

    One more thing to try could be to run the initialisation sequence from the datasheet again while observing the Vtune pin. This init sequence enables the frequency ramping, so you should be able to observe this on the Vtune pin; it will appear to be a sawtooth signal.

  • Ok good to know that you also think that the schematic and PCB layout should be fine. Do you know a PCB expert I could ask about the PCB design? Maybe there is a problem which is not that obvious. Bad grounding, interference with other modules on the board, or anything else...

    Yhea based on the measurements everything should work properly. Maybe I should assume that the chip has been damaged. Is it possible that the chip was damaged by short circuit of adjacent pins? Since this can easily happen when measuring the voltages. Or we overheated the chip somehow.

    I mean I have the components to assemble the second PCB. If I can be sure that everything with the PCB layout is fine, I will assemble the second board to eliminate the possibility of a damaged ADF5902. Or I try to replace the chip. But here the problem could be that I overheat the device by using a heat gun.

    No, I don't use a horn antenna. I just put an 50ohm cable on the spectrum analizer and hold the other side of the cable near to the transmission line. I know the coupling is anything but perfect, but I think it should be good enough to verify the output signal.

    I think I measured the Vtune pin before and can't observe the sawtooth signal. My explanation was that the decive doesn't start ramping until it detects the PLL is locked.

    Until now many thanks for your help! I really learned a lot during this troubleshooting process.

  • Hi,

    happy new year!

    I just went through the schematic of the evaluation board and found that there are two 1nF ac-coupling capacitors (C1, C2) sitting in front of the Ref_In input.

    I don't have no ac-coupling of the reference signal. It's the only point where my schematic differs from the evaluation board. Do you think that this could cause the problem?

  • Happy New Year to you too.

    I noticed that too, but in your first post you posted plots of the R divider and R div/2 outputs and they look OK.

     do you have any ideas?

  • Yes generally AC coupling is the safest bet to ensure the signal is at the correct bias internally, although if the reference oscillator is powered from the same supply rail as the PLL it can be okay to go without, hence why your muxout plots of N counter looked reasonable. It is still recommended to AC couple if possible. 

    In your lab picture above it doesn't look like you have provision for an external reference. In your schematic did you also include the series resistor on the reference output? I would try replacing this with a DC blocking capacitor.

    As for other things to try, I am kind of running out. One thing I just thought of, maybe you already tried this above and I missed it, but did you try different charge pump settings?

    Regards,

    Alex

  • Hi,

    i want to give a short update on my project. Last week I assembled my second PCB. I also added an AC-coupling capacitor (2200pF) for the reference oscillator signal. Unfortunately, the PLL does still not lock Disappointed

    The voltage supply seems to be ok. After the initialization sequence the Rset voltage is regulated to 623mV and VREG is at 1.88V. I also measured the current consumption of each subdevice before and after the initialization sequence.

    So the current consumption is a bit lower than expected, but the device seems to be programmed.

    Also the SPI communication works well, but I have now made a new observation. Both devices no longer have a RF output signal. With both devices I cannot write Register 1 and Register 17. All other registers are written correctly.

    I use the same initialization sequence which works on your device. After each step of the initialization sequence I write to Register 5 to make sure that also the double buffered registers are loaded. Then I write to Register 3 to set the Readback control. When I read register 1 after Step 15 I get:

    Step 15:
    Writing    -> Register : 1 | Value : 0 xFFF7FFE1
    Writing    -> Register : 5 | Value : 0 x1E28005
    Writing    -> Register : 3 | Value : 0 x1897843
    Reading -> Register : 1 | Value : 0 x140625E1  -> False

    the same in Step 20 when writing to Register 17:

    Step 20:
    Writing    -> Register : 17| Value : 0x11
    Writing    -> Register : 5  | Value : 0 x1E28005
    Writing    -> Register : 3  | Value : 0 x1897A43
    Reading -> Register : 17| Value : 0 x1000A031  ->  False

    Do you have an explanation for this?

    The device also will neither perform a calibration of the VCO nor the amplitude, since the calibration busy signal does not go high. Also the R and N divider signals are not present, when I use the MUXOUT control.

    Directly after assembling of the second PCB I made a quick and dirty measurement were I got the same RF output as in my earlier postings. But a few days later I got this error.

    Is the ADF5902 very sensitive to EMI? Maybe that will cause my problems.  I mean, it's surprising that sometimes I have a signal on the RF output and then on another day again not. I always used the same measurement setup.

    It is a pity that I could not get the module to work.

    Best regards,
    Philipp

  • Firstly, there is no need to write R5 after each register write, and this is probably affecting your ability to program the device correctly. You should only write R5 in the assigned points of the init sequence, or when updating the PLL frequency. The point of the double buffered registers is to stop the device from entering an invalid state when changing the PLL frequency. Please refer to section "PROGRAM MODES" on page 12 of the datasheet.

    Your measured supply currents are too low, which would indicate that the device is not being programmed correctly.

    • TX_AHI varies according to output power, but should be about 35 - 45 mA
    • DVDD & AHI combined should be about 10 mA
    • CP_AHI & VCO_AHI are as per your table (5 mA and ~85 mA)

    RF_AHI is the only measurement that looks correct.

    I can't explain why you are not reading back R1 and R17 correctly. Can you try again without writing to R5 each time?

    Is it possible to try this on a different setup or a different lab, or can you shut off other equipment in the lab or shield your board? I don't know about ADF5902's sensitivity to EMI, but there appears to be some variation in your setup if you are getting different results at different times.

Reply
  • Firstly, there is no need to write R5 after each register write, and this is probably affecting your ability to program the device correctly. You should only write R5 in the assigned points of the init sequence, or when updating the PLL frequency. The point of the double buffered registers is to stop the device from entering an invalid state when changing the PLL frequency. Please refer to section "PROGRAM MODES" on page 12 of the datasheet.

    Your measured supply currents are too low, which would indicate that the device is not being programmed correctly.

    • TX_AHI varies according to output power, but should be about 35 - 45 mA
    • DVDD & AHI combined should be about 10 mA
    • CP_AHI & VCO_AHI are as per your table (5 mA and ~85 mA)

    RF_AHI is the only measurement that looks correct.

    I can't explain why you are not reading back R1 and R17 correctly. Can you try again without writing to R5 each time?

    Is it possible to try this on a different setup or a different lab, or can you shut off other equipment in the lab or shield your board? I don't know about ADF5902's sensitivity to EMI, but there appears to be some variation in your setup if you are getting different results at different times.

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