ADF5902 PLL not locking


i'm just trying to figure out how i can get the ADF5902 to work. I have the exact same problems with the PLL as described in this post.

I'm also a student at the RWTH Aachen and writing my thesis on designing a radar shield for an Arduino. For this purpose i will use the ADF5902 in combination with the ADF5904. Niklas R, from the post above, was my predecessor and i thought i learned from his mistakes. But currently I am stuck with the same problem. 

So this time, we wanted to be on the safe side and kept to the reference design. So i choose a 100MHz reference oscillator (DSC1001) and use the same loop filter design as on the evaluation board for the ADF5902. If I try to look a single frequency at 24.1GHz, using this initialization procedure:

0x02000007, // R7   |    Master reset
0x0000002B, // R11  |    Reset the counters
0x0000000B, // R11  |    Enable counters
0x0018000D, // R13  |    Enable ramp divider
0x1D32A64A, // R10  |    Reserved 
0x2A20B929, // R9   |    VCO calibration setup
0x40003E88, // R8   |    Set the VCO frequency calibration divider clock to 500 -> 100 kHz
0x800FE520, // R0   |    Power up LO, ADC and VCO
// delay 10us
0x01800827, // R7   |    R = 1, double = 0, divider = 1, PFD = 50 MHz, CLK1 = 2048 => fPFD/CLK1 < 25kHz
0x00000006, // R6   |    Set the LSB FRAC = 0
0x01E28005, // R5   |    INT = 241, FRAC = 8388608, N = 241
0x00000004, // R4   |    AnalogTestBus = None -> Set the ATEST pin to high impedance
0x01897803, // R3   |    Sets the I/O level to 3.3 V, CAL_BUSY to MUXOUT
0x00020642, // R2   |    ADC_CLK_DIV = 50, Set ADC clock to 1 MHz
0xFFF7FFE1, // R1   |    Set the transmitter amplitude level to 8dBm
0x800FE720, // R0   |    VCO_Cal = 1, Start the VCO frequency calibration
// delay 1200us
0x800FE540, // R0   |    Turn Tx1 on, Tx2 off, and LO off
0x800FED40, // R0   |    Tx1 amplitude calibration
// delay 500us
0x800FE540, // R0   |    Turn Tx1 on, Tx2 off, and LO off
0x00000011, // R17  |    Reserved
0x0000000D, // R13  |    Clock divider off
0x004F000C, // R12  |    Charge pump current = 2.24 mA
0x2800B929, // R9   |    Normal Operation
0x0100A827, // R7   |    R = 1, double = 0, divider = 1, PFD = 50 MHz, CLK1 = 10
0x00000006, // R6   |    Set the LSB FRAC = 0
0x01E20005, // R5   |    PFD = 50 MHz, INT =241, MSB FRAC = 0; lock to 24.1 GHz
0x0189F803; // R3   |    Ramp Status tp Muxout, I/O voltage level to 3.3 V

In this example, I set the PFD frequency to 50MHz, but I also tried a PFD frequency of 10 0MHz. 

With that procedure i can measure an output signal with a bandwidth of around 4MHz and a peak at 24.1GHz, which obviously indicates a not perfect locked PLL. In this case the charge pump current  is set to 2.24mA. If i reduce the current to 0.28mA the bandwidth gets narrower, as you can see in the second image.

The voltages at the Rset and Vreg pin are also regulated well. If i look at the R_Divder, N_Divider or R_Divider/2, N_Divider/2 i can see the expected 50MHz signal,  respectivly 25MHz signal.



and both the R_Divider/2 and N_Divider/2 look similar:

So, i tried a lot of things but i'm running out of ideas. Do you have any suggestion what i can try next?

Thanks in advance!

Best regards, 


  • Are you using the same board as Niklas or have you done your own re-spin?



  • I have made a complete new design. As said, oriented to the reference design. 100MHz reference osciallator, same PLL loop design, the ADP7104 as power supply for the transmitter and the ADP150 for the oscillator. We put the decoupling capacitors as close as possible to the pins. This time, we really wanted to make sure the design would work.  

    I don't know, what we are doing wrong :/ Is it that complicated to make a working PCB design for this component?

  • I will try your init sequence with an eval board to rule that out. Although I am thinking the issue is with the loop filter since the RF input and REF input both look good going by your muxout plots.

    Are you uisng C0G/NP0 dielectric caps in the loop filter? Do you have the loop filter caps at either end of the filter close to the CP and vtune pins?

  • Ok, i looked it up. Only one of the capacitors is a C0G/NP0.

    100pF -> X7R

    220pF -> C0G/NP0

    3.3nF -> X7R

    I did't pay attention to the type of capacitors when selecting them.

    I think the caps should be close enough to the pins,  right?

    But if it really is the dielectric of the capacitors, that would be great. Then i will get some new ones.

    Another question concerns step 15 of the initialization sequence. Here the ADC clock divider is set, but bit 15 of register 2 is not set to one. So the ADC don't start the conversion.

    Do we need the ADC for the amplitude calibration of Tx1 and Tx2?

    What is meant by "ADC_Start: Normal operation" on page 18 of the datasheet?



  • Hi Phillipp,

    I cannot get our apps board programmed using your init sequence. I think the VCO or perhaps the Tx is not being correctly calibrated.

    I am trying to get time to figure out what the issue is with your sequence but in the meantime can you please try the init sequence exactly as it appears in the datasheet - So initialise for 24.025GHz, including the ramp config registers? 

    I am a bit confused about your question on step 15.Step 15 does not set the ADC divider, it selects the Tx calibration code which is used to select desired Tx output power. The Tx power is not actually set until the Tx conversion is run until step 18 and 20.

    The ADC conversion start bit in reg 2 is used when making a temperature readback (see DS page 33), so it is not required for the init sequence.