ADF 4356 signal interfere with transceiver output signal giving 10 MHz harmonic

The PLL output is proper when checked standalone at 6500 MHz, but when it is used as LO for an upconverter board the mixer output is having spurious and 10 MHz harmonics in passband at around 2.4 GHz. The register values, the image of the final output, and the stand-alone signal are attached.

Standalone PLL out,

Mixer out with 10MHz harmonic

Register values

Kindly guide us if we have missed any step or any test setup issue is there or any coupling issue and how to solve it.

  • Hi,

    It may be coupling through the supplies. Are you using separate or common supply for ADF4356, reference source and mixer? 

    Can you also try to change Register 4 as 0x30008984? 

    Kudret

  • All are connected to separate supplies, the reference source is VNA but the ground of all is not made common. We are unable to program it with register 4 values as you have suggested. Actually, we were using in single-ended mode till now with the configuration of differential. This we realized after you shared the register value. The register value you shared will change to single-ended mode but it is not happening. I have read in datasheet about ac coupling of ref in b to Agnd if unused, I am trying that now if it works with reference given at ref in a. Sorry for my ignorance, can you share how to do ac coupling of ref in B. Is the expected output from the ref in A+ or A-. Can you share the setting for the single-ended mode since we could not understand clearly from the data sheet regarding the setting for the single-ended mode (Hardware and Software)?

  • We could change the register value as you had shared. The settings are also done as per single ended mode. R6,r7 removed and r10,r15 to 50ohm. Output taken from A-. Pll out present but clock also present in final output as shared in post.

  • Hi,

    The spur may be coming from another source. Did you try to clock LO input of upconverter from a signal generator instead of ADF4356? 

  • yes that we tried with by feeding the clock from a VNA. The problem of interger boundart spurs have been solved the updating the loop filter to values as shown below, But now we want to improve the phase noise. The phase noise and loop filter details are as shown,

    For 10KHz and 100Khz this should have been much better. 

    Can you guide for the same, btw i created another thread for this issue since the subject is different now.