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HMC1121 Bias


What are the Idq limits for each stage assuming stages are biased separately?


  • The current into VDD2 will be significantly higher than the current into VDD1. However, we do not have much data where the currents are split out. I did find one data point where the device was biased to a total current of approx 1800 mA. In that case, IDD1 was around 800mA and IDD2 was around 1000 mA.

    The device was primarily characterized with VDD1 always connected to VDD2 and with VGG1 always connected to VGG2. So we don't recommend trying to bias the two stages separately. The amplifier was designed assuming that VGG1 would always be equal to VGG2. Separating VGG1 and VGG2 may work ok or it may get you into trouble with oscillations since you are taking the part