The frequency range for the RF_in signal of the ADF41020 PLL Synthesizer is defined as 4GHz to 18GHz both on the spec sheet and in the ADIsimPLL software (from "View Selector Guide").
However when designing a PLL in ADIsimPLL, I cannot select an output frequency in that range. I get the error message "PLL Min chip Frequency out of ADF41020 range".
After some testing, I realized I could only enter output frequencies in the range 16GHz to 72GHz (so the original range multiplied by a factor 4).
Why is that so? There is indeed a divide-by-4 module inside this chip, but the RF_in range is defined at the input of the chip, so before the divider which should then not be taken into account for the output frequency range of the PLL.
Because of this, I cannot simulate the evaluation board of this chip (with center frequency of 12GHz and PFD frequency of 2.5MHz).
Thank you for your help.