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ADF5356BCPZ random bad initialization

We are using ADF5356 to provide a range or Local Oscilator signals, 8 to 9.6 GHz, from its RFoutB port. 

We found a propper set of registers to lock oscilator to a common 100MHz reference signal.

4 PLLs are integrated in our devices, each one providing a fixed frequency but with some differences between them, at some configurations with 12.5 MHz PD freq or 25 MHz as PD freq. 

The problem comes when output signals suddenly presents high PD freq spurs modulated at both sides of the carrier. This unwanted behaviour only appears at some cases but it is unacceptable at the system. This behaviour also shows as a degradation at PN enlarging loop BW beyond desired. PLL keeps locked in any case, but randomly showing this unwanted behaviour.

PLL programming should be fine because PLL is working correctly most ot the times and most of the implementations. We are producing some series of around 10unis, and problem appears in an excesive 20% of them.

The way we use to detect the problem is switching on and off the unit several times. When the problem is hard enough you can find the unwanted behaviour from the very begining but some times we have to place the unit in a climatic chamber at 60ºC to discover the latent problem.

Solution found so far is to replace PLL for a new unit but this is short term solution.

I can give you further information when getting deeper in problem resolution.

Please advise... Any kind of help would be appreciated.

Thanks in advance.


Thread Notes

  • Hi Miguel,

    My understanding is the problem occurs only on some parts. Even for these problematic parts, problem does not always appear but you need to power off and on several times or even increase the ambient temperature. Is that correct?

    In each case when there occurs high PD spurs, the LBW characteristic is changing, right? I would say PD spur levels are increasing because the LBW widens and does not filter the spurs.

    Did you set the timeout values for the lowest fPFD or (increase the timeout values while decreasing the fPFD)? Can you try using higher timeout values?

    It would be great if you can provide some more info:

    - Is it possible to read the VCO core, band, bias values as explained in "VCO Readback Procedure" section in AN-1353 for both bad and good conditions for the same part?

    - A few PN and spectrum plots that shows the LBW and spurs for both failed and good conditions on same part?

    - Can you share the register settings and the loop filter configuration?

    If you can check these on multiple (say two) failed part, that would give more data to analyze.

    Regards, Kazim

  • Dear Kazim,

    Thank you very much for your answer. 

    Let me share some more info to clarify this effect.

    You are right, problem only occurs at some parts and some times but, we found some problematic parts in which the problem appear always, at some other we have to power on and off several times or increase device temp to force the faulty behaviour to appear. 

    You are right, as I wrote previously PD high spurs and increased LBW appears together when the faulty state occurs. LBW increases itself suddenly and PD spurs grow more than 30 dB (will get a screenshot as soon as posible). 

    We will check that time out you mentioned at our next step but did not check that so far.

    I will provide you with some more info as soon as I get that but I don't know yet if will be able to read that VCO status... will try to follow mentioned AN.

    By the way, find attached a PN plot with two different PN performances: faulty state (trace 2) and common operating (traces 1 and 3). The frequency shown is at IF band after down convertion from Ka-band. Find also attached a picture of the loop filter used.


    I will share tomorrow a copy of the registers set used.

    Thank you again for the support.

    Best Regards. 

  • Let me add promised registers set for 2 different configurations. 

    Looking forward to receiving your feedback.

    Thanks in advance

  • Hi Miguel,

    Are you using the directly the above register settings or following the routine explained in datasheet. Specifically ADC is disabled in GUI. That should be enabled and perform a valid conversion just before autocalibration.

    In your first mail, you said that "suddenly presents high PD freq spurs". It would be very surprising to see that LBW also widens abruptly without any programming or without any external impact. Is it possible to detect that change and how that happens.

    Any chance to read the VCO core, band, bias values?

    Regards, Kazim

  • Hi Kazim,

    Thank you very much for your answer. 

    I have to check programmed registers again, not only to check ADC enable value but also to play with timeout configuration, as you suggested at previous post. As far as I remember we used registers as shown at GUI so what could be the consecuences for a wrong value at ADC value?

    I couldn't get back to laboratory yet, I will try to read VCO core as soon as I can. 

    Changes at LBW and spurious performance are also surprising for me, thats why I asked for support, the only external event detected so far is the manual switching on/off process described. 

    Thank you in advance for your support. 

  • Dear kpeker,

    Let me use this thread to go deeper in this issue and go ahead with debugging. 

    Your advices were quite useful but not definitive. 

    From my last answer to now we have tested different PLL programming and getting the same or similar issue.

    We have enabled the ADC in all the registers sets for each desired frequency. That action was the key to get a good performance on ambient and high tempertures over the same design. We could avoid PFD frequency appearing on high temps start up and PN performance is OK.

    The problem now comes on lower temperatures, from -20 to -40°C. When we reach that temperatures at climatic chamber the equipment start showing PFD spurious at both sides of the carrier. The LBW shows also increased and PN performance starts being non compliant. 

    We could partially filter that PFD spurious adding a new pole on loop filter but the problem on PN performance is the same. Now the issue is not to filter the PFD spurious but to find out why VCO behaviour changes when operating at such low tempertures. 

    IT is not possible to read VCO core value or bias values on our design since we are using muxout pin as OC lock detect. 

    Please have a look to current registers set and kindly support us findind out what could be the rooto cause of such evolving PN/spurious performance. 

    Just to add some more information to the thread. 

    On high temperatures (+70ºC), LBW shortens on those synthetized frequencies with PFD = 12.5 MHz but that is not happening on those using higher PFD frequencies, 25 or 50 MHz. 

    Meanwhile, on low temperatures (-40ºC), LBW widens in all the sinthetized frequencies, either with PFD 12.5 MHz or higher. 

    Hope this could be usefull to find the root cause of this behaviour. 

    Thanks in advance. 

  • Can someone asist me on this topic?.

    I tried several configurations since the beguining of this thread. Some improvement has been achieved but still some questions pendant.

    Coudl you read my own answer made on Sep 29, 2023 6:05 PM in reply to kpeker.

    thanks in advance.