We are using ADF5356 to provide a range or Local Oscilator signals, 8 to 9.6 GHz, from its RFoutB port.
We found a propper set of registers to lock oscilator to a common 100MHz reference signal.
4 PLLs are integrated in our devices, each one providing a fixed frequency but with some differences between them, at some configurations with 12.5 MHz PD freq or 25 MHz as PD freq.
The problem comes when output signals suddenly presents high PD freq spurs modulated at both sides of the carrier. This unwanted behaviour only appears at some cases but it is unacceptable at the system. This behaviour also shows as a degradation at PN enlarging loop BW beyond desired. PLL keeps locked in any case, but randomly showing this unwanted behaviour.
PLL programming should be fine because PLL is working correctly most ot the times and most of the implementations. We are producing some series of around 10unis, and problem appears in an excesive 20% of them.
The way we use to detect the problem is switching on and off the unit several times. When the problem is hard enough you can find the unwanted behaviour from the very begining but some times we have to place the unit in a climatic chamber at 60ºC to discover the latent problem.
Solution found so far is to replace PLL for a new unit but this is short term solution.
I can give you further information when getting deeper in problem resolution.
Please advise... Any kind of help would be appreciated.
Thanks in advance.
Miguel