HMC8411 Instability

Hi AF95,

                Can you share the board layout and schematic?

Regards,

Jim B

Here you can find the top layer layout and the schematic. For what concerns the bottom layer, there are few power rails to bring the power to the ADL. Also when C3 is removed, the harmonics is still sustained.

Hi AF,

             I think the problem is layout related. I believe there is too much ground inductance. You need vias under the HMC8411 as shown in the attached  screen shot. Also the bias inductor should land directly on the RFOUT trace, the way it is layed out you have a stub with RF on it. L2 should land directly on the input trace as shown here in the attached.

You can review our Gerber files for reference. https://www.analog.com/media/en/technical-documentation/evaluation-documentation/gerber-files/HMC8411LP2FE_%20EVB_GERBER%20FILES.zip

Regards,

Jim B

Hi Jim, thanks for your kind reply.

I tried to manage a possible "handmade" solution. By scratching the microstrips I arranged to put the L2 on the trace but still the harmonic is present (but now it has 9dBm power instead of 11-12dBm) on the input.

With the demodulator connected, I can see the expected output but with an attenuation of more than 15dB! (and still A LOT of other frequency harmonics ranging from the expected one to 10-15GHz).

Best regards,

af 

Hi Jim, thanks for your kind reply.

I tried to manage a possible "handmade" solution. By scratching the microstrips I arranged to put the L2 on the trace but still the harmonic is present (but now it has 9dBm power instead of 11-12dBm) on the input.

With the demodulator connected, I can see the expected output but with an attenuation of more than 15dB! (and still A LOT of other frequency harmonics ranging from the expected one to 10-15GHz).

Best regards,

af 

Hi AF95,

            The missing vias will have an impact too. As ground inductance can cause amplifiers to oscillate.

Regards,

Jim B 

Thanks Jim. Do you have any suggestion to try recovering this layout? 

Also, could you suggest me any reference from which I can study those kind of problems, in order to avoid them in future projects?

Regards.

af

Hi AF95,

             Since the added vias need plating to connect to t the bottom ground plane I'm not sure the you can recover the current board you are testing.

ADI provides Gerber files of the EVBs. Reviewing them would be a good start.  Incorporate (as much as possible) the layout around the chip. We use grounded coplanar waveguide transmission lines with via fencing along the RF paths. Also as many vias under the chip as possible. This is both for thermal consideration and minimizing ground inductance. This becomes especially important at  higher frequencies.

This tutorial I found may be helpful.

https://www.printedcircuituniversity.com/index.php/pcb-design-layout-placement/142-a-practical-guide-to-rf-and-microwave-pcb-design

This article cover layout considerations. The board discussed is a 4 layer board. The concepts apply to 2 layer board

https://www.analog.com/media/en/technical-documentation/application-notes/layout_guidelines_for_mmic_components.pdfs as well.

Regards,

Jim B