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ADRF6650 PLL doesn't lock on evaluation board


I'm using ADRF6650-EVALZ board and ACE software but I did not succeed to get DS1 on or LOCK_DETECT register set to 1 meaning PLL is locked. 

My RF reference signal is a sinus at 15.36MHz and 2.5Vpp in order to obtain 30.73MHz thanks the input multiplier. Is it a good reference signal ?

Which parameter is influenced by the Ch spacing ?

What is the right programming cycle to process a PLL initialization ?

Thank you for your future answer.

Kind regards,


Wrong tags
[edited by: adrienINVOLI at 7:36 AM (GMT -4) on 15 Sep 2021]