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ADRF6650 PLL doesn't lock on evaluation board


I'm using ADRF6650-EVALZ board and ACE software but I did not succeed to get DS1 on or LOCK_DETECT register set to 1 meaning PLL is locked. 

My RF reference signal is a sinus at 15.36MHz and 2.5Vpp in order to obtain 30.73MHz thanks the input multiplier. Is it a good reference signal ?

Which parameter is influenced by the Ch spacing ?

What is the right programming cycle to process a PLL initialization ?

Thank you for your future answer.

Kind regards,


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[edited by: adrienINVOLI at 7:36 AM (GMT -4) on 15 Sep 2021]
Parents Reply
  • Hello,

    As reference signal I generate a sinus of 20MHz and 1.5Vpp.  Afterwards, I multiply it by 2 to obtain a 40MHz as signal input of PFD.
    On the PLL side, I have a CP current of 2.4mA and I enable the bleed with a PFD offset of 2 ns.

    Mind to send all these values before change "int_L" register and start the PLL lock process.

    I hope that will help you,

    Best regards,


  • Dear Adrien

    Thank you for your kind reply.

    I tried again with your advice, but still have same trouble.

    I used follow setup for registers.

    REF_IN : sinusoidal 20MHz

    0x120E : 0x08 (DOUBLER_IN is 1 for 40MHz PFD, RDIV2_SEL is 0)

    0x120C : 0x01 (R_DIV is 1)

    0x1201 : 0x00 (INT_H is 0)

    0x1200 : 0x90 (INT_L is 144, I set this register at the last of sequence following DS and your advice)

    0x1202, 0x1203, 0x1204 : 0x00 (FRAC1 is 0)

    0x1233, 0x1234 : 0x00 (FRAC2 is 0)

    0x1209 : 0x00, 0x1208 : 0x02 (MOD is 2)

    0x122A : 0x20 (SD_EN_FRAC0 is 1, SD_EN_OUT_OFF is 0, SD_SM_2 is 0)

    0x122E : 0x07 (CP_CURRENT is 2.4mA)

    0x122F : 0x00 (BICP is 0, I am not sure about this value actually)

    If you give me any advice, it will be great help for me.

    Best regards

    Sangkyun Kim