ADRF6650 PLL doesn't lock on evaluation board

Question

Hello, 
 
 I'm using ADRF6650-EVALZ board and ACE software but I did not succeed to get DS1 on or LOCK_DETECT register set to 1 meaning PLL is locked. 
 
 My RF reference signal is a sinus at 15.36MHz and 2.5Vpp in order to obtain 30.73MHz thanks the input multiplier. Is it a good reference signal ? 
 Which parameter is influenced by the Ch spacing ? 
 What is the right programming cycle to process a PLL initialization ? 
 
 Thank you for your future answer. 
 
 Kind regards, 
 
 Adrien

rachana.kaza@analog.com · Accepted Answer

Hi Adrien, 
 Your reference signal does meet all the requirements for REF_IN. 
 MOD and FRAC2 are the parameters that are affected by Channel spacing. 
 Please refer Required PLL/VCO Settings and Register Write Sequence section on Page 27 of the DS:. 
 Configure the PLL registers accordingly to achieve the desired frequency, and the last write must be to Register 0x1200 (INT_L). When Register 0x1200 is programmed, an internal VCO calibration initiates, which is the last step to locking the PLL. After the PLL locks, enable the buffer to the mixer via the MIX_OE bit (Register 0x1414, Bit 7) to provide the LO signal to the mixer. External LO. 
 Hope this helps. 
 Warm Regards, 
 Rachana

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ADRF6650 PLL doesn't lock on evaluation board

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