ADRF6650 PLL doesn't lock on evaluation board

Hello,

I'm using ADRF6650-EVALZ board and ACE software but I did not succeed to get DS1 on or LOCK_DETECT register set to 1 meaning PLL is locked. 

My RF reference signal is a sinus at 15.36MHz and 2.5Vpp in order to obtain 30.73MHz thanks the input multiplier. Is it a good reference signal ?

Which parameter is influenced by the Ch spacing ?

What is the right programming cycle to process a PLL initialization ?

Thank you for your future answer.

Kind regards,

Adrien



Wrong tags
[edited by: adrienINVOLI at 7:36 AM (GMT -4) on 15 Sep 2021]
  • 0
    •  Analog Employees 
    on Sep 23, 2021 6:29 PM

    Hi Adrien,

    Your reference signal does meet all the requirements for REF_IN.

    MOD and FRAC2 are the parameters that are affected by Channel spacing.

    Please refer Required PLL/VCO Settings and Register Write Sequence section on Page 27 of the DS:.

    Configure the PLL registers accordingly to achieve the desired frequency, and the last write must be to Register 0x1200 (INT_L). When Register 0x1200 is programmed, an internal VCO calibration initiates, which is the last step to locking the PLL. After the PLL locks, enable the buffer to the mixer via the MIX_OE bit (Register 0x1414, Bit 7) to provide the LO signal to the mixer.
    External LO.

    Hope this helps.

    Warm Regards,

    Rachana

  • Hi Rachana,

    You are right, it was our reference signal which didn't met all the requirements.

    Thank you for your help, really useful !

    Adrien

  • Hello Adrien

    I have similar trouble with ADRF6650 for the PLL lock.

    If you don't mind, could you give me your register values for reference?

    Best regards

    Sangkyun Kim

  • Hello,

    As reference signal I generate a sinus of 20MHz and 1.5Vpp.  Afterwards, I multiply it by 2 to obtain a 40MHz as signal input of PFD.
    On the PLL side, I have a CP current of 2.4mA and I enable the bleed with a PFD offset of 2 ns.

    Mind to send all these values before change "int_L" register and start the PLL lock process.

    I hope that will help you,

    Best regards,

    Adrien

  • Dear Adrien

    Thank you for your kind reply.

    I tried again with your advice, but still have same trouble.

    I used follow setup for registers.

    REF_IN : sinusoidal 20MHz

    0x120E : 0x08 (DOUBLER_IN is 1 for 40MHz PFD, RDIV2_SEL is 0)

    0x120C : 0x01 (R_DIV is 1)

    0x1201 : 0x00 (INT_H is 0)

    0x1200 : 0x90 (INT_L is 144, I set this register at the last of sequence following DS and your advice)

    0x1202, 0x1203, 0x1204 : 0x00 (FRAC1 is 0)

    0x1233, 0x1234 : 0x00 (FRAC2 is 0)

    0x1209 : 0x00, 0x1208 : 0x02 (MOD is 2)

    0x122A : 0x20 (SD_EN_FRAC0 is 1, SD_EN_OUT_OFF is 0, SD_SM_2 is 0)

    0x122E : 0x07 (CP_CURRENT is 2.4mA)

    0x122F : 0x00 (BICP is 0, I am not sure about this value actually)

    If you give me any advice, it will be great help for me.

    Best regards

    Sangkyun Kim