ADRF6650 Programming

Hello,

I am developing a linux driver for the ADRF6650 and am having some difficulty accessing certain registers.

I seem to be able to read/write the majority of registers, but am unable to write to the PLL registers, ie.  the MOD, FRACx, INT, etc. registers.

No matter what I write to them, they always return zero.

Is there some enable bit or sequence that I am missing?

Regards



EDIT: Just to be clear, I am accessing the ADRF6650 on an Eval board that has been successfully tested and programmed using ADI's ACE controller software. My issue seems to be that I cannot access any register 0x1021 and above. All registers 0x0000 to 0x0310 can be written and read without any trouble.
[edited by: mrush at 5:40 PM (GMT -4) on 8 Sep 2021]
  • +1
    •  Analog Employees 
    on Sep 10, 2021 6:53 PM

    HI,

    DO you see a LO signal or lock detect to be high when you complete the PLL programming?

    On Pg#27 of the DS, Under  this dection "Required PLL/VCO Settings and Register Write Sequence", it mentions that we need to write to register0X1200 to complete the programming of  the PLL and for the INT, FRAC & MOD values to be applied to the part.


    Configure the PLL registers accordingly to achieve the desired frequency, and the last write must be to Register 0x1200 (INT_L). When Register 0x1200 is programmed, an internal VCO calibration initiates, which is the last step to locking the PLL. After the PLL locks, enable the buffer to the mixer via the MIX_OE bit (Register 0x1414, Bit 7) to provide the LO signal to the mixer.

    Just to confirm that you are not setting Bit 7 in this ,Register 0x0102 to be 1 which disables the PLL/VCO.

    The ADRF6650 also provides TDD enable masks to enable/ disable certain blocks during TDD operation. The TDD enable masks select which blocks are disabled during TDD off time. The EN_MASK register (Register 0x0102) includes the mask bits for the LO stages, the IF amplifiers, the DVGAs, and the PLL. When set to 1, the bits shown in Table 17 disable the related block during TDD off time. The enable mask bits for the LO Stage 23, the IF amplifiers, and the DVGA disable the related block (when set to 1) when either one of the TDD_A and TDD_B pins is set to high. Alternatively, the LO_STG1_ ENB_MASK bit (Register 0x0102, Bit 0) disables the LO stage amplifier only when both TDD_A and TDD_B are high. In the same manner, the PLL_ENB_CH12_MASK bit (Register 0x0102, Bit 7) disables the PLL/VCO only when both TDD_A and TDD_B are high.

    Hope this helps.

    Warm Regards,

    Rachana

  • My apologies.  The board I was testing on had been damaged during our testing.  Repaired the board and it is working now.