I am trying to use ADF4001 to synchronize a 100MHz VCXO to an external 100MHz reference signal(from a TCXO with Kv=330Hz/V), and I set the PFD at 200KHz with loop bandwidth around 445Hz.
I used ADIsimPLL to calculate the loop filter and ADI PLL Int-N to calculate the register, but I found it don't get latched.
then I try to change the PFD to 100KHz、50KHz and 25KHz with no hardware changes, then it get latched, but with a very long time.(about several hundred ms to 1s)
that's made me confused that if that's normal and if the ADIsimPLL is with guiding significance.
the attachment is the ADIsimPLL file, please help m4001e to check if there are something wrong with the hardware or register code?
the hardware maybe correct because i copied it from other 10MHz latch 100MHz project. and i checked that it's power supply is correct.