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Why is the simulation of ADF4001 very different from the actual？



		

			

									
						Amvolt.Smile
					
							

			
				
									
											
							 		
		        	            							
			
			    	
			                    
                
				                on Sep 7, 2021 
				
			
			
		


				
		

		    		    
		    
		    	
			
I am trying to use ADF4001 to synchronize a 100MHz VCXO to an external 100MHz reference signal(from a TCXO with Kv=330Hz/V), and I set the PFD at 200KHz with loop bandwidth around 445Hz.


I used ADIsimPLL to calculate the loop filter and ADI PLL Int-N to calculate the register, but I found it don't get latched.


then I try to change the PFD to 100KHz、50KHz and 25KHz with no hardware changes, then it get latched, but with a very long time.(about several hundred ms to 1s)


that's made me confused that if that's normal and if the ADIsimPLL is with guiding significance.


the attachment is the ADIsimPLL file, please help m4001e to check if there are something wrong with the hardware or register code?


the hardware maybe correct because i copied it from other 10MHz latch 100MHz project. and i checked that it's power supply is correct.


  



1050.ADF 4001.rar

								


				
				
		

			
						
									
									
						
						
			
			
			
			
		


					

			





	










	

	

					



			








	
	
	
	



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                                 Analog Employees 
                                
                            
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                on Sep 7, 2021 10:14 AM
            
            
					
    
	
    

		
		
    
					
    Hello,
    

    

    With a very narrow loop bandwidth the PLL will take a very long time to settle. This is one of the trade offs for the narrow cutoff frequency in the loop filter. With LBW < 1kHz a settle time of 5ms or more is not unexpected. 
    

    In your ADIsimPLL simulation you have set the CP current for the sim = 5mA whereas you have programmed the CP current = 2.5mA which explains why the part wouldn't lock at first since with CP current = 2.5mA the loop filter you have designed could be somewhat unstable due to reduced phase margin. I would recommend changing the programmed CP current to 5mA to match closer to the sim
    

    Regards,
    

    Alex
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
						
						
				
				
		
		
    
			
		
    
	
    

    

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                on Sep 8, 2021 2:27 AM
            
            
												
						in reply to aandrews
					
									
    
	
    

		
		
    
					
    Thanks for your reply！
    

    I found that the CP current doesn't effect the loop filter, and I had tried to change the CP current，but it doesn't effect the result.
    

    what made me confused is that why the simulation latch time is so different from the real latch time? the real latch time is about several hundred ms to 1s.
    

    and i just wanna know if the degree that simulation matches the reality is normal? 
    

    many thanks！
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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                                 Analog Employees 
                                
                            
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                on Sep 9, 2021 12:30 PM
            
            
												
						in reply to Amvolt.Smile
					
									
    
	
    

		
		
    
					
    Hi, Generally ADIsimPLL lock time measurement is fairly accurate so >100ms does sound long. How are you measuring the lock time, are you looking at lock detect or are you measuring vtune?
    

    I think since you have problems locking at the designed PFD frequency and changing the CP current does not change some filter response there is some hardware problem. Is there some leakage or noise on the CP line? On your board layout do you have C1 close to the ADF4001 CP pin and C2 close to vtune pin of VCXO?
    

    BTW, how come you do not use ADF4002? It supports 100MHz PFD and N = 1 so you could get better performance with a much lower N value.
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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													0
							
			
				
									
							        
            
                                                                                                        
      
                            
    • 
                                 Analog Employees 
                                
                            
      • 
                        
     
                                                           			
			                            
                        
                on Sep 9, 2021 12:30 PM
            
            
												
						in reply to Amvolt.Smile
					
									
    
	
    

		
		
    
					
    Hi, Generally ADIsimPLL lock time measurement is fairly accurate so >100ms does sound long. How are you measuring the lock time, are you looking at lock detect or are you measuring vtune?
    

    I think since you have problems locking at the designed PFD frequency and changing the CP current does not change some filter response there is some hardware problem. Is there some leakage or noise on the CP line? On your board layout do you have C1 close to the ADF4001 CP pin and C2 close to vtune pin of VCXO?
    

    BTW, how come you do not use ADF4002? It supports 100MHz PFD and N = 1 so you could get better performance with a much lower N value.
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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