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ADF4360-1 behavior at 2098 MHz (edge of VCO bands) during REFin drift

Hi,

How would ADF4360-1 behave when frequency is set to 2098 MHz (which is right on the edge of VCO bands) and REFin is drifting within +-1% (see picture from the datasheet below). Will it lose lock or switch the VCO band? 

Regards,
Ivan

  • Ivan,  That is a typical plot of typical part at typical temperature.  That VCO transitions in the plot will vary some over Process Voltage and Temperature.  I have not worked on the ADF4360 directly, but I'm going to assume its VCO calibration is like our other PLL/VCO parts.  Basically, the integrated PLL/VCOX have a a lot of narrow band VCOs, and the VCO calibration uses the reference frequency, PLLs Ref divider, and PLLs N or feedback divider to select a VCO that will work for the desired frequency.  So any change to the reference frequency, the Ref divider, or N divider will result in a new desired frequency, which will usually require a new VCO calibration to find the correct VCO for the new desired frequency.

    From your description, it sounds like the customer is sweeping the reference frequency +/-1% to change the output frequency +/-1?  Typically these integrated PLL/VCOs are not great for frequency sweep applications due to the VCO calibration process.  For most sweep applications we recommend a stand alone PLL, with a wider band VCO that covers the desired frequency range of the sweep.  

    Maybe something like the HMC586 with the LTC6947 w/ integrated output divider would work?

    Chris

  • Yes, you are right. The customer is sweeping the reference frequency within +/-1%. But their main question is how ADF4360-1 would behave in the case I described earlier. Would it work correctly or would it loss of lock?

    There were a lot of design team efforts done to design in the ADF4360. There is no chance to change the PLL now.

    I don't have ADF4360-1 evaluation board to check the described behavior. Do you have ability to check ADF4360-1 behavior on your evaluation board?

    Regards,
    Ivan

  • Typically, this is not something we guarantee/encourage with our integrated PLL/VCOs.  I am checking to see if anyone from that development team has any specific knowledge if we can guarantee this.

    The problem as I tried to describe above is the variation frequency ranges in process, temperature and supply voltage. This will change the Vtune vs frequency locations for each VCO band.  

    Do you have any idea of what temperature range and power supply voltage range they designed for? 

  • Temp range is something between -40C and +70C. Supply voltage is 3.3V.

    Also I know that temperature and other factors change Vtune vs Frequency graph. I just would like to clarify ADF4360 behavior on the edge of VCO bands once PLL frequency has locked. I would appreciate it if you could clarify this.

  • Thanks.  After speaking with the development team. We only guarantee frequency coverage for an output frequency that was determined by the VCO calibration.  Any change in reference frequency would be cause to start a new VCO calibration.  For this customer if they sweep the reference they run the risk of losing lock as they approach either edge of the VCO band.  

  • Hi Chris,

    Thank you for the clarification.

    Regards,
    Ivan