HI Analog team,
We are trying to generate 800 to 1312MHz LO signal from ADF4350 PLO. Step size shall be 10KHz.
We are using 24.576MHz LVCMOS clock as a reference.
Below are the schematic and register values used.
With this settings, we are unable to get lock at any frequency. If we set it at 800MHz,we are getting 798.8MHz output and if we set it at 1300MHz, we are getting 2271MHz. And LD and muxout pin are always low.
We have throughly checked SPI timings and it is fine. Using this SPI we are able to control RF output enable disable and RF power level and other things.
Please review our design and let us if any issue.