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Signal Behavior on HMC832 VTUNE Pin

Dear Madam/Sir:

                          This is a query regarding the observance of signal on VTUNE pin of HMC832A. Upon updating the PLL output frequency from the GUI provided with the evaluation board of HMC832A, a low pulse of duration of the order of tens of milli-seconds is captured by oscilloscope. Along with VTUNE signal, the SDO signal is also held low during the same time. It is also noted that the VTUNE signal falls gradually within few micro-seconds at falling edge of the pulse, and it rises gradually and settles to about 1.8V at the rising edge of the pulse. I sincerely request to you to provide explanation for this behavior yet not understood. I am, herewith, attaching the screenshots of the observations. The VTUNE and SDO signals, as shown in screenshots, are of green and yellow color respectively. Thank you.



Format corrected.
[edited by: RSB at 2:14 PM (GMT -4) on 11 Aug 2021]
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  • Hi,

    SDO pin is used for various functionalities: Lock detect, serial data out and GPO. It can also be dynamically mux'ed between LD and SDO. Please see Table 11 in the datasheet. From the screenshots it looks like reading the register when SCLK is active and LD otherwise. While part is locking, LD is low and once it is locked pin is logic high.

    Regards, Kazim

  • Thank you, for answering. I actually wanted to know the answers to the following questions:

    1. What is happening on the VTUNE pin upon updating PLL? (Why does it go low for milli-seconds of time duration?)

    2. When VTUNE pin goes low upon updating PLL, what is the behavior at PLL output pin? (Is there signal still available on output pin even when VTUNE is low upon updating PLL output frequency? If yes, is it the same frequency as the previously updated value?)

    3. Can the PLL output frequency settling time be measured on oscilloscope using VTUNE pin while using LD pin as trigger source? (In first screenshot, the VTUNE pin rises from zero and settles to a steady value. And in about the same time LD goes high. Can the time elapsed between the instant when VTUNE voltage starts to rise and the instant when LD goes high, be taken as output frequency settling time?)

    Thank you.

  • Hi,

    1. Once autocalibration is initiated the VTune pin is disconnected from the internal VCO tune port (so the loop is broken) and VCO is forced to near the mid-voltage of CP. The autocalibration may take a few milliseconds (even higher) depending on the configuration. This is explained in "VCO Calibration" section in the datasheet.

    2. In autocalibration process, part is not locked, indeed part is searching the correct frequency. Hence the VCO frequency is not stable. The output buffers can be set to be muted automatically when the part is not locked from VCO_REG 0x03[8:7]

    3. The instant when the VTUNE voltage starts to rise is the point where internal VCO tune port is connected to external VTUNE pin and loop is established again. This may be considered as loop settling time. But note that there will be some latency and uncertainities both in Vtune rising and the time where lock detect goes high. Basically that depends on the accuracy you need.

    For the total lock time for changing frequency the autocalibration time should be added as well. If you need fast frequency settling, you should use Manual VCO calibration which is explained in the datahseet on page 20.

    Regards, Kazim

  • Thank you very much. Your answer helped increase my understanding further, on the HMC832 functioning. With reference to your answer, I would like to know that can auto-calibration time be as large as to be in order of tens of milli-seconds? In the second picture I posted, the VTune signal is low for about 16ms. Is this the auto-calibration time of my PLL? [I have kept the register settings as default, R=1, and used external reference oscillator of 10MHz.]

    Thank you.

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  • Thank you very much. Your answer helped increase my understanding further, on the HMC832 functioning. With reference to your answer, I would like to know that can auto-calibration time be as large as to be in order of tens of milli-seconds? In the second picture I posted, the VTune signal is low for about 16ms. Is this the auto-calibration time of my PLL? [I have kept the register settings as default, R=1, and used external reference oscillator of 10MHz.]

    Thank you.

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