ADF4158 power supply sequence

Hi everybody,

I'd like to supply the charge pump of the ADF4158 with Vp = 5V (Vdd = 3.3V), but I have the requirement that 5V comes after 3.3V.

It appears as this would violate the specs as per the datasheet:

VP  AVDD to 5.5 V

In the Absolute Maximum Ratings there is a statement about Vp relative to Vdd but that doesn't make much sense to me.

So can anybody clarify whether it is allowed for Vp to be ramped up after Vdd?

Best regards

Jens.

Update:
Just one additional thing. The power supply spec stating Vp = AVdd to 5.5 V probably just refers to the nominal (i.e. working) condition.
That's why I was also looking at the Absolute Maximum Ratings where are two limitations WRT to Vp. The first is: Vp to GND = -0.3 V to +5.8 V; and the second one is: Vp to Vdd = -0.3 to 5.8 V,. But the latter one seems to be very misleading at least.



Clarification on Absolute Maximum Ratings.
[edited by: jensrenner at 11:03 AM (GMT -4) on 2 Aug 2021]
  • +2
    •  Analog Employees 
    on Aug 6, 2021 1:46 PM

    Hi Jens,

    You are correct in your update that the "VP = AVDD to 5.5 V" from the spec table is more for showing the voltage range the values in the spec table are tested to meet, under normal operation.

    We generally recommend that AVDD and Vp come up reasonably close to the same time. On page 8 of datasheet you should note that the pin description of Vp states it should be greater than or equal to Vdd. 

    With that said, the AMR spec states there is a wide range allowable in Vp to Vdd so it is probably not going to damage the device if you bring Vdd up first. How long after Vdd does Vp supply come up in your implementation?

    Regards,

    Alex

  • Hi Alex,

    Thanks for taking the time to answer and sorry for the late response (I haven't been notified about your comment).

    It makes totally sense to me what you are writing. Unfortunately the time from powering up Vdd until Vp comes up could be indefinitely long as Vdd = 3.3V would be the "stand-by supply" to retain the register settings, and Vp would be brought up only at certain times when the PLL is actually in use.

    That's why I made the decision to use 3.3V for Vp as well to avoid any issues, and instead go for a higher OpAmp gain to cover a wider range of Vtune.

    Thanks & regards

    Jens.

  • 0
    •  Analog Employees 
    on Sep 13, 2021 1:37 PM in reply to jensrenner

    Hi Jens,

    No problem, thanks for the update! And I think you made the right call to edit the design slightly to ensure Vp and AVDD came up closer together. No worries using an op amp with ADF4158, I've seen a few successful, long term designs with this part that use an active loop filter.

    Regards,

    Alex