ADF5902: PLL not locking for CW

Hi,

I am trying to get my PLL to lock, but have been unsuccessful in trying different register writes/loop filter configurations. My sequence/loop filter is listed below can you see any potential error with my configuration? I am able to get tones close to my signal(24.069GHz usually) but don't get a lock. I suspect it has something to do with the write sequence, I am using the ADF5902 software to manually write in the values.

Frequency=24.125GHz

REFin=19.2MHz

write sequence:

 parameter r0  = 32'h02000007;  // R7

   parameter r1  = 32'h0000002B;  // R11

   parameter r2  = 32'h0000000B;  // R11

   parameter r3  = 32'h0018000D;  // R13

   parameter r4  = 32'h1D32A64A;  // R10

   parameter r5  = 32'h2A20B929;  // R9

   parameter r6  = 32'h40003E88;  // R8

   parameter r7  = 32'h800FE520;  // R0

    // #10us

   parameter r8  = 32'h01620427;  // R7

   parameter r9  = 32'h00000006;  // R6

   parameter r10 = 32'h01E28005;  // R5

   parameter r11 = 32'h00000004;  // R4

   parameter r12 = 32'h01897803;  // R3

   parameter r13 = 32'h00020642;  // R2

   parameter r14 = 32'hFFF7FFE1;  // R1

   parameter r15 = 32'h800FE720;  // R0

    // #1200us

   parameter r16 = 32'h800FE560;  // R0

   parameter r17 = 32'h800FED60;  // R0

    // #500us

   parameter r18 = 32'h800FE5A0;  // R0

   parameter r19 = 32'h800FF5A0;  // R0

    // #500us

   parameter r20 = 32'h00000011;  // R17

   parameter r21 = 32'h00000010;  // R16

   parameter r22 = 32'h0000000D;  // R14

   parameter r23 = 32'h2800B929;  // R9

   parameter r36 = 32'h01620427;  // R7

   parameter r37 = 32'h00000006;  // R6

   parameter r38 = 32'h01E28005;  // R5

   parameter r39 = 32'h00002004;  // R4

   parameter r40 = 32'h0189F803;  // R3

   parameter r41 = 32'h801FE560;  // R0

   // #100us

   parameter r42 = 32'h0000110B;  // R11

   parameter r43 = 32'h01E28005;  // R5

Loop filter:

leveraged previous questions:

https://ez.analog.com/rf/f/q-a/546031/adf5902-pll-not-locking

https://ez.analog.com/rf/f/q-a/544087/adf5902-cannot-be-locked

Top Replies

    •  Analog Employees 
    Jul 29, 2021 +2 verified

    As  mentioned, you are missing a write to R12 to enable the charge pump current.

    The INT & FRAC settings need to be updated for your reference frequency, ref doubler & divider settings. Refer to…

Parents
  • +1
    •  Analog Employees 
    on Jul 29, 2021 11:30 AM

    As  mentioned, you are missing a write to R12 to enable the charge pump current.

    The INT & FRAC settings need to be updated for your reference frequency, ref doubler & divider settings. Refer to "RF SYNTHESIS: A WORKED EXAMPLE" on page 33 of the datasheet.

    The VCO needs to be calibrated with fVCO = 24.175 GHz to ensure the part can operate across the full frequency range (24 - 24.25 GHz). This is not explicit in the datasheet, although it is implied based on the values of R5 - R7 in steps 9 - 11 of the init sequence.
    Additionally, the Frequency Calibration Divider setting in R8, the Clock Divider setting in R7 and ADC Clock Divider setting in R2 must be set correctly during calibration. Refer to respective register maps in the datasheet for details.

    Try the following sequence, which should lock the PLL to 24.125 GHz with output on TX1. All values hexadecimal.

    02000007
    0000002B
    0000000B
    0018000D
    1D32A64A
    2A20B929
    40003008	// VCO_freq_cal_divider = 384
    800FE520
    // wait 10us
    01600427	// clk_divider1 = 1536; rdoubler = 1 (fpfd = 38.4 MHz) => fpfd/clk1 = 25 kHz
    00015546	// frac_lsb = 2730
    02758EA5	// intn = 314; frac_msb = 3189
    00000004
    01897803
    000204C2	// ADC_clk_divider = 38 => ADC clock = ~1MHz
    FFF7FFE1
    800FE720 	// start VCO calibration
    // wait 1200us
    800FE560
    800FED60	// start tx1 amplitude calibration
    // wait 500us
    800FE5A0
    800FF5A0	// start tx2 amplitude calibration
    // wait 500us
    800FE560	// tx1 & lo outputs enabled; tx2 disabled
    00000011
    0000000D
    004F000C	// charge pump current = 2.24mA (setting 7)
    2800B929
    01000427
    0002AAA6	// frac_lsb = 5461
    02744145	// intn = 314; frac_msb = 522

Reply
  • +1
    •  Analog Employees 
    on Jul 29, 2021 11:30 AM

    As  mentioned, you are missing a write to R12 to enable the charge pump current.

    The INT & FRAC settings need to be updated for your reference frequency, ref doubler & divider settings. Refer to "RF SYNTHESIS: A WORKED EXAMPLE" on page 33 of the datasheet.

    The VCO needs to be calibrated with fVCO = 24.175 GHz to ensure the part can operate across the full frequency range (24 - 24.25 GHz). This is not explicit in the datasheet, although it is implied based on the values of R5 - R7 in steps 9 - 11 of the init sequence.
    Additionally, the Frequency Calibration Divider setting in R8, the Clock Divider setting in R7 and ADC Clock Divider setting in R2 must be set correctly during calibration. Refer to respective register maps in the datasheet for details.

    Try the following sequence, which should lock the PLL to 24.125 GHz with output on TX1. All values hexadecimal.

    02000007
    0000002B
    0000000B
    0018000D
    1D32A64A
    2A20B929
    40003008	// VCO_freq_cal_divider = 384
    800FE520
    // wait 10us
    01600427	// clk_divider1 = 1536; rdoubler = 1 (fpfd = 38.4 MHz) => fpfd/clk1 = 25 kHz
    00015546	// frac_lsb = 2730
    02758EA5	// intn = 314; frac_msb = 3189
    00000004
    01897803
    000204C2	// ADC_clk_divider = 38 => ADC clock = ~1MHz
    FFF7FFE1
    800FE720 	// start VCO calibration
    // wait 1200us
    800FE560
    800FED60	// start tx1 amplitude calibration
    // wait 500us
    800FE5A0
    800FF5A0	// start tx2 amplitude calibration
    // wait 500us
    800FE560	// tx1 & lo outputs enabled; tx2 disabled
    00000011
    0000000D
    004F000C	// charge pump current = 2.24mA (setting 7)
    2800B929
    01000427
    0002AAA6	// frac_lsb = 5461
    02744145	// intn = 314; frac_msb = 522

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