adisimpll locked frequency does not equal design frequency

Hello , I want to use ADF4371 to produce a range of equal spaced output frequencie in 4GHz to 6GHz , but When the PLL is stabilized, the VCO output frequency (the locking frequency) is not equal to the design frequency, as shown in the picture.

Design1.zip

  • When you have a PLL that covers a range of frequencies, you will find that the loop gain varies as you change the VCO frequency (due to variations in Kv, and N).  What ADIsimPLL does is to choose one 'average' VCO frequency and designs the loop filter.  We called this the 'Design Frequency'. You can then analyse the PLL at other frequencies - this is the Analysis Frequency, set in the Freq Domain folder.  You can simulate a transient as you doing, the initial and final frequencies for the transient simulation are set in the Time Domain folder.

    If you right clicked on the Design Freq entry and chose "What's this", ADIsimPLL would display the helpfile entry.