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# why the phase noise for the RF/16,RF/2 and RF of HMC739 are different?

Dear support:

I have designed a PLL  with ADF4150HV + HMC739, the configuration of  ADF4150HV and loop filter I have used were listed below.

Reference input clock of ADF4150HV is 25Mhz

D=0, R=2, T=0, so the f_PFD=12.5 MHz,

RF Divider=1, FRAC=0, INT= 122,  so the RF output is 1.525 GHz * 16 =24.4 GHz

Loop filter BW=50kHz, phase margin = 45 degree, and a 4th order filter model was used.

With the above configuration, the VCO HMC739 successfully produce a 24.4 GHz signal, but its phase noise looks very bad. I also measured the spectrum of the RF/16 and RF/2, and the spectrum of RF/16=1.525 GHz is much better than the one of RF = 24.4 GHz. The pictures below are spectrum of RF/16, RF/2 and RF signals of HMC739.

Q1:  why the phase noise for RF/16, RF/2 and RF of HMC739 are different?

Q2:  Is there any way to reduce the phase noise of the RF output?

I appreciate if someone can help me with my puzzle. Thanks a lot!

Parents
• Can you please send the ADIsimPLL file of your specific loop filter design, or a schematic? What model of reference are you using?

• Hi,

Thank you for pay attention to my question! I have solved this problem and my board is working now.

I previously ignored whether the supply voltage of HMC739 meets the requirement on the datasheet, I tested this voltage by chance and found that it is 4.2V, which is smaller than the minimum value of 4.75V specified in the datasheet. Then I increase this supply voltage to 4.8V and all the problems were solved.

Thanks again.

Reply
• Hi,

Thank you for pay attention to my question! I have solved this problem and my board is working now.

I previously ignored whether the supply voltage of HMC739 meets the requirement on the datasheet, I tested this voltage by chance and found that it is 4.2V, which is smaller than the minimum value of 4.75V specified in the datasheet. Then I increase this supply voltage to 4.8V and all the problems were solved.

Thanks again.

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