we are working on a beam forming application in certain ISM bands and I have selected the ADF4351 as a synthesizer chip.
Currently we have two chips which share the same reference clock.
The idea was that we can run the ADF4351 in a mode where we have a known phase difference between the two ADF4351 chips.
Our reference clock is 16 MHz and distributed via a clock buffer to the two ADF4351.
So far we are able to generate a signal at 910 MHz on both synthesizer chips.
It seems also that we keep the phase difference after the power on when changing frequency.
But as soon as we power ON/OFF the chip we end if with a different phase.
1) So far we have tried to run in FRAC mode and use the resync feature. But this did not work all the time.
What we did was setting the PLL and then setting the re-sync bit.
2) Second approach was to run in integer mode and keep the FRAC register 0. This mode should end up to our understanding
with a stable phase difference between the synthesizers but it does not. Also activating the re-sync does not help.
Our current integer mode configuration looks the following:
16 MHz reference clock
"FRAC/MOD GCD" is OFF
// 910 MHz R=160 spacing = 10 4/5
R = 0x11C60000;
R = 0x8051;
R = 0x280E42;
R = 0x963;
R = 0x201024;
R = 0x580005;
A) Our first question is: Can you confirm that with this synthesizer it is possible to have two chips which always have the same phase difference with respect to each other when changing frequency and when power cycling?
B) Would it be possible to provide a working example with stable phase difference for lets say 910 MHz or close to it.
C) What is the exact way to use the re-sync feature, in case this is meant for this purpose.
D) In case such a mode exist where the phase difference is stable between the two chips, is it possible in this mode to then after the PLL is locked change the phase by the PHASE register?
Thank for helping