Stable relative phase between two ADF4351

Hi,

we are working on a beam forming application in certain ISM bands and I have selected the ADF4351 as a synthesizer chip.

Currently we have two chips which share the same reference clock.

The idea was that we can run the ADF4351 in a mode where we have a known phase difference between the two ADF4351 chips.

Our reference clock is 16 MHz and distributed via a clock buffer to the two ADF4351.

So far we are able to generate a signal at 910 MHz on both synthesizer chips.

It seems also that we keep the phase difference after the power on when changing frequency.

But as soon as we power ON/OFF the chip we end if with a different phase.

1) So far we have tried to run in FRAC mode and use the resync feature. But this did not work all the time.

What we did was setting the PLL and then setting the re-sync bit.

2) Second approach was to run in integer mode and keep the FRAC register 0. This mode should end up to our understanding

with a stable phase difference between the synthesizers but it does not. Also activating the re-sync does not help.

Our current integer mode configuration looks the following:

16 MHz reference clock

"FRAC/MOD GCD" is OFF

   // 910 MHz R=160 spacing = 10 4/5
        R[0] = 0x11C60000;
        R[1] = 0x8051;
        R[2] = 0x280E42;
        R[3] = 0x963;
        R[4] = 0x201024;
        R[5] = 0x580005;

A) Our first question is: Can you confirm that with this synthesizer it is possible to have two chips which always have the same phase difference with respect to each other when changing frequency and when power cycling?

B) Would it be possible to provide a working example with stable phase difference for lets say 910 MHz or close to it.

C) What is the exact way to use the re-sync feature, in case this is meant for this purpose.

D) In case such a mode exist where the phase difference is stable between the two chips, is it possible in this mode to then after the PLL is locked change the phase by the PHASE register?

Thank for helping

Best regards

Daniel

Parents
  • +1
    •  Analog Employees 
    on Jul 12, 2021 8:18 AM

    Hi,

    Phase re-sync does not guarantee a constant phase relation with the reference in each power-up. Phase resync ensures same phase at the output clock when frequency is changed and set to the previous frequency again. 

    Let me put this with a usage scenario like that: Two parts are at the same frequency and phase re-sync is enabled for both of them. There is a phase relation between those two part (can be zero or some constant value). If the frequency of these parts are changed and set back to the initial frequency value, their phase relation will stay same with the initial condition. This is how phase resync works. 

    Your expectation for integer mode operation is correct as long as reference divider value is 1 and feedback loop is taken from the divided output. You are using divided output as your feedback signal but you are using reference divider value of 16. Output of the reference divider can take any phase value of (360/16) in that case and it can be (possibly will) different with multiple parts. If you can try an integer frequency with a reference divider value of 1, you'll see that phase relation between two parts will remain constant. 

    Below is two app note that explains phase adjust, phase resync features in detail. Especially first note is a good example how to solve the initial phase error between multiple parts and how to create a feedback loop. 

    Phase Alignment and Control on the ADF4356/ADF5356 Devices | Analog Devices

    (+) ADF4350 Phase Resync - Q&A - RF and Microwave - EngineerZone (analog.com)

    Kudret

Reply
  • +1
    •  Analog Employees 
    on Jul 12, 2021 8:18 AM

    Hi,

    Phase re-sync does not guarantee a constant phase relation with the reference in each power-up. Phase resync ensures same phase at the output clock when frequency is changed and set to the previous frequency again. 

    Let me put this with a usage scenario like that: Two parts are at the same frequency and phase re-sync is enabled for both of them. There is a phase relation between those two part (can be zero or some constant value). If the frequency of these parts are changed and set back to the initial frequency value, their phase relation will stay same with the initial condition. This is how phase resync works. 

    Your expectation for integer mode operation is correct as long as reference divider value is 1 and feedback loop is taken from the divided output. You are using divided output as your feedback signal but you are using reference divider value of 16. Output of the reference divider can take any phase value of (360/16) in that case and it can be (possibly will) different with multiple parts. If you can try an integer frequency with a reference divider value of 1, you'll see that phase relation between two parts will remain constant. 

    Below is two app note that explains phase adjust, phase resync features in detail. Especially first note is a good example how to solve the initial phase error between multiple parts and how to create a feedback loop. 

    Phase Alignment and Control on the ADF4356/ADF5356 Devices | Analog Devices

    (+) ADF4350 Phase Resync - Q&A - RF and Microwave - EngineerZone (analog.com)

    Kudret

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