ADF5902 PLL not locking

Hey,

after following the instructions of another post of mine (https://ez.analog.com/rf/f/q-a/538009/using-adf4159-for-a-cw-radar-application/396330#396330), I tried to get the ADF5902 running this week. Im trying to lock the ADF5902 to a single frequency (no ramps), but cant get it to work. When using a spectrum analyzer I see the signal over a wide bandwith:

Im using the initialization sequence (via SPI) mentioned in the datasheet (slighty modified, by neglecting the writes to register R13-R16 as mentioned here: https://ez.analog.com/rf/f/q-a/544087/adf5902-cannot-be-locked) and setting the frequency to 24.1 GHz with the following:

  • 20 MHz Oscillator
  • Reference Doubler D=1
  • Reference division factor R= 1
  • Reference divide by 2 bit T=0
  • N=301
  • F_MSB =1024
  • F_LSB=0

Here ist the sequence:

0x02000007	// R7
0x0000002B	// R11
0x0000000B	// R11
0x1D32A64A	// R10
0x2A20B929	// R9
0x40003E88	// R8
0x800FE520	// R0

// delay of 10 microseconds

0x01800827	// R7
0x00000006	// R6
0x01E38005	// R5
0x00000004	// R4
0x01897803	// R3
0x00020642	// R2
0xFFF7FFE1	// R1
0x800FE720	// R0

// delay of 1200 microseconds

0x800FE560	// R0
0x800FED60	// R0

// delay of 500 microseconds

0x800FE5A0	// R0
0x800FF5A0	// R0

// delay of 500 microseconds

0x00000011	// R17
0x004F000C	// R12
0x2800B929	// R9
0x01800427	// R7; here i deploy my pll settings
0x00000006	// R6
0x025A8005	// R5
0x00002004	// R4
0x0189F803	// R3

// delay of 100 microseconds

0x0000010B	// R11

The used loop-filter:

What I tried so far:

  • using a different ADF5902 Chip
  • using a recalibration sequence
  • changing the pfd frequency by disabling the referncy doubler
  • setting the center frequency to a different frequency
  • measured the 20 MHz Oscillator (works fine)

So far, nothing helped. I would really appreciate if someone could help me with this issue.

If you need any other information, please let me know!

Parents
  • 0
    •  Analog Employees 
    on Jun 11, 2021 5:39 PM

    You still need to write to R13 during the VCO calibration setup to enable the clock divider (step 4 in datasheet init sequence). You should omit the later writes to setup the ramp divider (steps 31 - 34 in datasheet init sequence) and replace with a write to R13 to turn the clock divider off (0x0000000D).

    I have edited my post in the other thread to clarify this.

  • Thanks for the quick reply. Im going to test this on monday and will report on the the outcome!

  • 0
    •  Analog Employees 
    on Jun 16, 2021 6:32 PM in reply to Niklas R

    The N & R divider plots look more or less as expected. I am not sure why your Tx1 output is not locked.

    I tested the sequence I gave you on our customer eval board today with a 20 MHz external reference. The Tx1 output was locked to 24.1 GHz as expected.

    Init sequence log:

    adf5902_init_fref_20MHz_fpfd_40MHz_fout_24100MHz_no_ramp_TXout1_log.txt
    18:46:41: Writing 0x2000007
    18:46:41: 0x2000007 written to ADF5902
    18:46:49: Writing 0x2B
    18:46:49: 0x2B written to ADF5902
    18:47:01: Writing 0xB
    18:47:01: 0xB written to ADF5902
    18:47:10: Writing 0x18000D
    18:47:10: 0x18000D written to ADF5902
    18:47:19: Writing 0x1D32A64A
    18:47:19: 0x1D32A64A written to ADF5902
    18:47:28: Writing 0x2A20B929
    18:47:28: 0x2A20B929 written to ADF5902
    18:47:37: Writing 0x40003E88
    18:47:37: 0x40003E88 written to ADF5902
    18:47:46: Writing 0x800FE520
    18:47:46: 0x800FE520 written to ADF5902
    18:47:55: Writing 0x1640427
    18:47:55: 0x1640427 written to ADF5902
    18:48:05: Writing 0x6
    18:48:05: 0x6 written to ADF5902
    18:48:13: Writing 0x25C6005
    18:48:13: 0x25C6005 written to ADF5902
    18:48:20: Writing 0x4
    18:48:20: 0x4 written to ADF5902
    18:48:28: Writing 0x1897803
    18:48:28: 0x1897803 written to ADF5902
    18:48:36: Writing 0x20502
    18:48:36: 0x20502 written to ADF5902
    18:48:43: Writing 0xFFF7FFE1
    18:48:43: 0xFFF7FFE1 written to ADF5902
    18:48:51: Writing 0x800FE720
    18:48:51: 0x800FE720 written to ADF5902
    18:48:59: Writing 0x800FE540
    18:48:59: 0x800FE540 written to ADF5902
    18:49:07: Writing 0x800FED40
    18:49:07: 0x800FED40 written to ADF5902
    18:49:16: Writing 0x800FE540
    18:49:16: 0x800FE540 written to ADF5902
    18:49:24: Writing 0x11
    18:49:24: 0x11 written to ADF5902
    18:49:32: Writing 0xD
    18:49:32: 0xD written to ADF5902
    18:49:40: Writing 0x4F000C
    18:49:40: 0x4F000C written to ADF5902
    18:49:50: Writing 0x2800B929
    18:49:50: 0x2800B929 written to ADF5902
    18:49:59: Writing 0x1000427
    18:49:59: 0x1000427 written to ADF5902
    18:50:07: Writing 0x6
    18:50:07: 0x6 written to ADF5902
    18:50:15: Writing 0x25A8005
    18:50:15: 0x25A8005 written to ADF5902
    18:50:25: Writing 0x189C803
    18:50:25: 0x189C803 written to ADF5902

    I think now may be the time to try a new loop filter design. Could you modify your board with the design I sent previously?

  • May I ask what loop filter desing you used? The same as in the ADISimPLL-File? I haven't change the parts yet, as it will probably be my last resort.

  • 0
    •  Analog Employees 
    on Jun 17, 2021 8:35 AM in reply to Niklas R

    I used the EV-ADF5902SD1Z customer evaluation board to test the sequence. The loop filter schematic is on page 12 of the user guide (link). But this loop filter is designed for a 100MHz reference/PFD frequency, which is why the signal appears a bit noisy on the spectrum analyser plot that I posted.

  • Hi,

    sorry it has been a while as I was busy writing my master thesis. After we swapped to a new Loop filter design with a 100 MHz Oscillator, the problem could still be observed. We then tested the supply signals as well as the Charge pump output:

    There is a huge ripple on both signals (blue=VCC; yellow=charge pump), which is probably causing the unexpected output of the resulting spectrum. We could not identify the source of this noise. However, this periodic ripple is probably coupling on the chargepump (or vice versa) because the PCB layout has a resistor of the loop filter placed right above a supply line. See here:

     .

    We gonna discard this PCB for now and put our focus on the corresponding receiver board.

    The receiver PCB utilises the ADF5902 to generate a LO-signal for downconversion. As we were testing the PCB, we could see that the PLL was once again not locking and the VCO was just wandering around a certain bandwith (no distribution like above mentioned).  When we analysed this new problem, we could see that there was actually no charge pump output at all. The basic circuitry and initialisation sequence is exactly the same, but this behaviour is only present for the receiver PCB. Do you have any idea why the charge pump output is not working correctly? We checked every supply voltage pin, as well as the oscillator. Would really appreciate your help once more:) Thanks in advance!

  • 0
    •  Analog Employees 
    on Aug 6, 2021 1:15 PM in reply to Niklas R

    Is it possible for you to measure the current draw of CP_AHI? It should be approx. 5mA with the device locked to the default init sequence at 3.3V supply and ambient temperature.

    It's possible that the device could have been damaged during assembly. Do you have another receiver board that you can try?

    An unlikely possibility is that an ADF5901 device has been installed by mistake. The pinout of this device is the same as ADF5902, except for the CP supply and output pins. Please check that the marking of the device is 'ADF5902WCCPZ'.

Reply
  • 0
    •  Analog Employees 
    on Aug 6, 2021 1:15 PM in reply to Niklas R

    Is it possible for you to measure the current draw of CP_AHI? It should be approx. 5mA with the device locked to the default init sequence at 3.3V supply and ambient temperature.

    It's possible that the device could have been damaged during assembly. Do you have another receiver board that you can try?

    An unlikely possibility is that an ADF5901 device has been installed by mistake. The pinout of this device is the same as ADF5902, except for the CP supply and output pins. Please check that the marking of the device is 'ADF5902WCCPZ'.

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