ADF5902 PLL not locking

Hey,

after following the instructions of another post of mine (https://ez.analog.com/rf/f/q-a/538009/using-adf4159-for-a-cw-radar-application/396330#396330), I tried to get the ADF5902 running this week. Im trying to lock the ADF5902 to a single frequency (no ramps), but cant get it to work. When using a spectrum analyzer I see the signal over a wide bandwith:

Im using the initialization sequence (via SPI) mentioned in the datasheet (slighty modified, by neglecting the writes to register R13-R16 as mentioned here: https://ez.analog.com/rf/f/q-a/544087/adf5902-cannot-be-locked) and setting the frequency to 24.1 GHz with the following:

  • 20 MHz Oscillator
  • Reference Doubler D=1
  • Reference division factor R= 1
  • Reference divide by 2 bit T=0
  • N=301
  • F_MSB =1024
  • F_LSB=0

Here ist the sequence:

0x02000007	// R7
0x0000002B	// R11
0x0000000B	// R11
0x1D32A64A	// R10
0x2A20B929	// R9
0x40003E88	// R8
0x800FE520	// R0

// delay of 10 microseconds

0x01800827	// R7
0x00000006	// R6
0x01E38005	// R5
0x00000004	// R4
0x01897803	// R3
0x00020642	// R2
0xFFF7FFE1	// R1
0x800FE720	// R0

// delay of 1200 microseconds

0x800FE560	// R0
0x800FED60	// R0

// delay of 500 microseconds

0x800FE5A0	// R0
0x800FF5A0	// R0

// delay of 500 microseconds

0x00000011	// R17
0x004F000C	// R12
0x2800B929	// R9
0x01800427	// R7; here i deploy my pll settings
0x00000006	// R6
0x025A8005	// R5
0x00002004	// R4
0x0189F803	// R3

// delay of 100 microseconds

0x0000010B	// R11

The used loop-filter:

What I tried so far:

  • using a different ADF5902 Chip
  • using a recalibration sequence
  • changing the pfd frequency by disabling the referncy doubler
  • setting the center frequency to a different frequency
  • measured the 20 MHz Oscillator (works fine)

So far, nothing helped. I would really appreciate if someone could help me with this issue.

If you need any other information, please let me know!

Parents
  • 0
    •  Analog Employees 
    on Jun 11, 2021 5:39 PM

    You still need to write to R13 during the VCO calibration setup to enable the clock divider (step 4 in datasheet init sequence). You should omit the later writes to setup the ramp divider (steps 31 - 34 in datasheet init sequence) and replace with a write to R13 to turn the clock divider off (0x0000000D).

    I have edited my post in the other thread to clarify this.

  • Thanks for the quick reply. Im going to test this on monday and will report on the the outcome!

  • 0
    •  Analog Employees 
    on Jun 13, 2021 10:02 PM in reply to Niklas R

    I've edited your sequence to update some values during the cal sequence:

    • CLK1 must be set so that fpfd/clk1 is <=25 kHz
    • ADC clock divider must be set so that ADC clock is 1 MHz
    • VCO should be calibrated with fvco = 24.175 GHz

    Please try this out and let me know if it works. I haven't tested this sequence in the lab.

    adf5902_init_fref_20MHz_fpfd_40MHz_fout_24100MHz_no_ramp.txt
    0x02000007	// R7
    0x0000002B	// R11
    0x0000000B	// R11
    0x0018000D	// R13	// clock divider enabled for vco calibration
    0x1D32A64A	// R10
    0x2A20B929	// R9
    0x40003E88	// R8
    0x800FE520	// R0 
    // delay of 10 microseconds
    0x01640427	// R7	// clk1 = 1600; rdoubler = 1 (fpfd = 40 MHz) => fpfd/clk1 = 25 kHz
    0x00000006	// R6	// frac_lsb = 0
    0x025C6005	// R5	// int = 302; frac_msb = 768
    0x00000004	// R4
    0x01897803	// R3
    0x00020502	// R2	// adc clk div = 40
    0xFFF7FFE1	// R1
    0x800FE720	// R0 
    // delay of 1200 microseconds
    0x800FE560	// R0
    0x800FED60	// R0 
    // delay of 500 microseconds
    0x800FE5A0	// R0
    0x800FF5A0	// R0 
    // delay of 500 microseconds
    0x00000011	// R17
    0x0000000D	// R13	// clock divider off
    0x004F000C	// R12
    0x2800B929	// R9
    0x01000427	// R7	// rdoubler = 1 (fpfd = 40 MHz); clk1 = 0 (ramp mode not used)
    0x00000006	// R6	// frac_lsb = 0
    0x025A8005	// R5	// int = 301; frac_msb = 1024
    0x0189C803	// R3 	// muxout = ndiv/2 (optional write - may be useful for debug)

  • Thank you.

    I will test this sequence tomorrow!

  • Hi again,

    unfortunately the sequence posted by you, didn't work either. The result was the same as mentioned above. As I tried almost anything code-wise, I was wondering if I made a mistake designing the Loop Filter. If you don't have anymore suggestions for the initialization sequence, I would really appreciate if you could take a look on the design (created with ADISimPLL) and if I did something wrong:

    Report:

    Schematic:

    Components:

    Frequency Domain:

    Time Domain:

    Is there a specific Loop Filter Design that you can recommend? And would switching to a different PFD-Frequency be advisable?

    I'm running out of options to solve my problem and would be really grateful for any kind of advise. Thanks!

Reply
  • Hi again,

    unfortunately the sequence posted by you, didn't work either. The result was the same as mentioned above. As I tried almost anything code-wise, I was wondering if I made a mistake designing the Loop Filter. If you don't have anymore suggestions for the initialization sequence, I would really appreciate if you could take a look on the design (created with ADISimPLL) and if I did something wrong:

    Report:

    Schematic:

    Components:

    Frequency Domain:

    Time Domain:

    Is there a specific Loop Filter Design that you can recommend? And would switching to a different PFD-Frequency be advisable?

    I'm running out of options to solve my problem and would be really grateful for any kind of advise. Thanks!

Children
  • 0
    •  Analog Employees 
    on Jun 14, 2021 3:48 PM in reply to Niklas R

    Is it possible for you to attach the *.PLL file generated by ADIsimPLL? If not, I will try to recreate your loop filter design.

    Could you also attach the schematic for your board please?

    Some things to check:

    • Check the values for the capacitors connected to the C1, C2 and VREG pins match the datasheet values (pages 7 - 8). VREG output should be 1.8V to 1.9V.
    • Do you have a 5.1k resistor to ground connected to the RSET pin? This sets the charge pump current. Nominal voltage on this pin should be 0.62V.
  • The Values of C1,C2 & VREG, RSET are the same as in the sheet. I can test the exact values (and voltage) on our board tomorrow to validate this.

    Here is the schematic (ADF5902 Part):

    VCC is driven by an external source, followed by a Buck-Converter (to 3.3V) and an additional LDO.

    I dont have the option to attach a file to this post. I have uploaded it to a filehoster (PW: adf5902):

    https://easyupload.io/fiogyf

    If you need anything else, please let me know. Thanks again!

  • +1
    •  Analog Employees 
    on Jun 15, 2021 9:56 AM in reply to Niklas R

    I'm no expert in loop filter design, but I had a look at your file and changed some settings:

    • Changed PFD frequency to 40 MHz
    • Changed loop filter bandwidth to 100 kHz

    This generated the filter below:

    ADIsimPLL file in ZIP below:

    adf5902_lpf_100kHz_fref_20MHz_fpfd_40MHz.zip

    However, before you go changing loop filter components on your board, there are a couple of things to try.

    • Init sequence is setup to output on TXout2, but I noticed that you are only using TXout1. You can skip the TXout2 amplitude calibration and replace with a write to power up TXout1 and power down the TXout2 & LOout outputs
      • See updated init sequence below.
    • Try increasing or decreasing the charge pump current setting (bits[DB20:DB17] in R12 - see page 26 of datasheet)
      • Note that R5 must be written after R12 for the charge pump settings to take effect (refer to page 12 of datasheet)
    • Try disabling the doubler when locking the PLL after running the VCO and TXout1 calibrations
      • The INT and FRAC values in R5 & R6 will need to be updated if you do this, as fPFD will now be equal to fREF = 20 MHz
      • Note: keep the doubler enabled during the VCO frequency calibration

    4087.adf5902_init_fref_20MHz_fpfd_40MHz_fout_24100MHz_no_ramp_TXout1.txt
    0x02000007	// R7
    0x0000002B	// R11
    0x0000000B	// R11
    0x0018000D	// R13	// clock divider enabled for vco calibration
    0x1D32A64A	// R10
    0x2A20B929	// R9
    0x40003E88	// R8
    0x800FE520	// R0 
    // delay of 10 microseconds
    0x01640427	// R7	// clk1 = 1600; rdoubler = 1 (fpfd = 40 MHz) => fpfd/clk1 = 25 kHz
    0x00000006	// R6	// frac_lsb = 0
    0x025C6005	// R5	// int = 302; frac_msb = 768
    0x00000004	// R4
    0x01897803	// R3
    0x00020502	// R2	// adc clk div = 40
    0xFFF7FFE1	// R1
    0x800FE720	// R0 	// start VCO calibration
    // delay of 1200 microseconds
    0x800FE540	// R0	// power up TXout1; power down TXout2 & LOout
    0x800FED40	// R0 	// start TXout1 amplitude calibration
    // delay of 500 microseconds
    0x800FE540	// R0	// disable TXout1 amplitude calibration (optional write)
    0x00000011	// R17
    0x0000000D	// R13	// clock divider off
    0x004F000C	// R12	// charge pump current setting 7 = 2.24mA
    0x2800B929	// R9
    0x01000427	// R7	// rdoubler = 1 (fpfd = 40 MHz); clk1 = 0 (ramp mode not used)
    0x00000006	// R6	// frac_lsb = 0
    0x025A8005	// R5	// int = 301; frac_msb = 1024
    0x0189C803	// R3 	// muxout = ndiv/2 (optional write - may be useful for debug)

    What decoupling do you have on the supply pins? Ideally there should be 10pF, 1nF and 100nF decoupling caps close to the pins. See page 13 of the eval board user guide.

    Is your reference source AC coupled? i.e. DC blocking cap in series

  • Thanks for your effort!

    Let me first answer your questions from the post before:

    • V(R_set) = 0.632 V
    • V(V_reg) = 1.884 V
    • Value of R_set on my board is 5.088 kOhm
    • Values of capacitors should be within 1% of desired value

    Now your last post:

    • altering the Chargepump current had no major impact
    • i tried the PLL with PFD=20MHz and the issue unfortunately persisted (also changed the values of R6 & R5)
    • i have the 10pf, 1nF and 100 nF decoupling caps on my board (each set ist close to the respected pins)
    • my reference source doesnt have dc blocking caps in series

  • 0
    •  Analog Employees 
    on Jun 15, 2021 11:28 AM in reply to Niklas R

    Did you try the updated init sequence I provided to enable output on TXout1?

    What are the details of your reference source?