ADF5902 PLL not locking

Hey,

after following the instructions of another post of mine (https://ez.analog.com/rf/f/q-a/538009/using-adf4159-for-a-cw-radar-application/396330#396330), I tried to get the ADF5902 running this week. Im trying to lock the ADF5902 to a single frequency (no ramps), but cant get it to work. When using a spectrum analyzer I see the signal over a wide bandwith:

Im using the initialization sequence (via SPI) mentioned in the datasheet (slighty modified, by neglecting the writes to register R13-R16 as mentioned here: https://ez.analog.com/rf/f/q-a/544087/adf5902-cannot-be-locked) and setting the frequency to 24.1 GHz with the following:

  • 20 MHz Oscillator
  • Reference Doubler D=1
  • Reference division factor R= 1
  • Reference divide by 2 bit T=0
  • N=301
  • F_MSB =1024
  • F_LSB=0

Here ist the sequence:

0x02000007	// R7
0x0000002B	// R11
0x0000000B	// R11
0x1D32A64A	// R10
0x2A20B929	// R9
0x40003E88	// R8
0x800FE520	// R0

// delay of 10 microseconds

0x01800827	// R7
0x00000006	// R6
0x01E38005	// R5
0x00000004	// R4
0x01897803	// R3
0x00020642	// R2
0xFFF7FFE1	// R1
0x800FE720	// R0

// delay of 1200 microseconds

0x800FE560	// R0
0x800FED60	// R0

// delay of 500 microseconds

0x800FE5A0	// R0
0x800FF5A0	// R0

// delay of 500 microseconds

0x00000011	// R17
0x004F000C	// R12
0x2800B929	// R9
0x01800427	// R7; here i deploy my pll settings
0x00000006	// R6
0x025A8005	// R5
0x00002004	// R4
0x0189F803	// R3

// delay of 100 microseconds

0x0000010B	// R11

The used loop-filter:

What I tried so far:

  • using a different ADF5902 Chip
  • using a recalibration sequence
  • changing the pfd frequency by disabling the referncy doubler
  • setting the center frequency to a different frequency
  • measured the 20 MHz Oscillator (works fine)

So far, nothing helped. I would really appreciate if someone could help me with this issue.

If you need any other information, please let me know!

Parents Reply Children
  • 0
    •  Analog Employees 
    on Jun 13, 2021 10:02 PM in reply to Niklas R

    I've edited your sequence to update some values during the cal sequence:

    • CLK1 must be set so that fpfd/clk1 is <=25 kHz
    • ADC clock divider must be set so that ADC clock is 1 MHz
    • VCO should be calibrated with fvco = 24.175 GHz

    Please try this out and let me know if it works. I haven't tested this sequence in the lab.

    adf5902_init_fref_20MHz_fpfd_40MHz_fout_24100MHz_no_ramp.txt
    0x02000007	// R7
    0x0000002B	// R11
    0x0000000B	// R11
    0x0018000D	// R13	// clock divider enabled for vco calibration
    0x1D32A64A	// R10
    0x2A20B929	// R9
    0x40003E88	// R8
    0x800FE520	// R0 
    // delay of 10 microseconds
    0x01640427	// R7	// clk1 = 1600; rdoubler = 1 (fpfd = 40 MHz) => fpfd/clk1 = 25 kHz
    0x00000006	// R6	// frac_lsb = 0
    0x025C6005	// R5	// int = 302; frac_msb = 768
    0x00000004	// R4
    0x01897803	// R3
    0x00020502	// R2	// adc clk div = 40
    0xFFF7FFE1	// R1
    0x800FE720	// R0 
    // delay of 1200 microseconds
    0x800FE560	// R0
    0x800FED60	// R0 
    // delay of 500 microseconds
    0x800FE5A0	// R0
    0x800FF5A0	// R0 
    // delay of 500 microseconds
    0x00000011	// R17
    0x0000000D	// R13	// clock divider off
    0x004F000C	// R12
    0x2800B929	// R9
    0x01000427	// R7	// rdoubler = 1 (fpfd = 40 MHz); clk1 = 0 (ramp mode not used)
    0x00000006	// R6	// frac_lsb = 0
    0x025A8005	// R5	// int = 301; frac_msb = 1024
    0x0189C803	// R3 	// muxout = ndiv/2 (optional write - may be useful for debug)

  • Thank you.

    I will test this sequence tomorrow!

  • Hi again,

    unfortunately the sequence posted by you, didn't work either. The result was the same as mentioned above. As I tried almost anything code-wise, I was wondering if I made a mistake designing the Loop Filter. If you don't have anymore suggestions for the initialization sequence, I would really appreciate if you could take a look on the design (created with ADISimPLL) and if I did something wrong:

    Report:

    Schematic:

    Components:

    Frequency Domain:

    Time Domain:

    Is there a specific Loop Filter Design that you can recommend? And would switching to a different PFD-Frequency be advisable?

    I'm running out of options to solve my problem and would be really grateful for any kind of advise. Thanks!

  • 0
    •  Analog Employees 
    on Jun 14, 2021 3:48 PM in reply to Niklas R

    Is it possible for you to attach the *.PLL file generated by ADIsimPLL? If not, I will try to recreate your loop filter design.

    Could you also attach the schematic for your board please?

    Some things to check:

    • Check the values for the capacitors connected to the C1, C2 and VREG pins match the datasheet values (pages 7 - 8). VREG output should be 1.8V to 1.9V.
    • Do you have a 5.1k resistor to ground connected to the RSET pin? This sets the charge pump current. Nominal voltage on this pin should be 0.62V.
  • The Values of C1,C2 & VREG, RSET are the same as in the sheet. I can test the exact values (and voltage) on our board tomorrow to validate this.

    Here is the schematic (ADF5902 Part):

    VCC is driven by an external source, followed by a Buck-Converter (to 3.3V) and an additional LDO.

    I dont have the option to attach a file to this post. I have uploaded it to a filehoster (PW: adf5902):

    https://easyupload.io/fiogyf

    If you need anything else, please let me know. Thanks again!