ADL5304 PCB Layout design rules

Hi there,

I am new to the design of this transimpedance amplifier PCB layout. I have seen the waveguide-like layout for Inum and Iden input currents. And also Vsm is passing parallel to these tracks in the Evaluation board for ADL5304. I can also observe the bare PCB (without masking) in this Inum, Vsm, and Iden region. Also, there are many through-holes are poured all over the PCB. This observation of mine leads me to ask the rules for this specific layout design rules. I also want to learn how this helps to measure the very small current and the noise immunity. Please someone guide me. I want to get a thorough understanding. The reference image is shown below.

  • 0
    •  Analog Employees 
    on May 31, 2021 11:46 PM

    Hi,

    I moved your question to its proper community.

    Regards.

  • +1
    •  Analog Employees 
    on Jun 1, 2021 11:31 PM

    Hello Tikull,

    The ADL5304 PCB layout utilizes guard traces adjacent to the input traces. These traces are at approximately same electrical potential as the inputs themselves, therefore leakage current is substantially reduced. Furthermore , layer 2 of PCB is also connected to the guard potential, again to minimize leakage. Consider the math: for example, a hypothetical insulation resistance of 15,000 Meg Ohms seems like a lot, but with voltage difference of 1.5V from input to ground, leakage_I= 1.5V/15G = 100pA, a huge DC offset for the ADL5304, and easily measurable. 

    Notice the solder mask removed from the input trace area, which helps increase resistance, and reduce capacitance of the input trace to ground. These devices and the circuits that use them can be quite sensitive to capacitance, and often require very short input traces designed for very low capacitance. 

    Vias along the guard trace connect to the guard trace beneath. Extra vias help reduce the area that would be subject to magnetic field pickup, which could come from nearby switching power supplies for example. 

    Input impedance is very high, and in normal usage the device is very sensitive to electrostatic noise pickup, especially as input current gets lower. Down at the lowest current levels measured in pA and nA, a simple grounded electrostatic shield may be needed above the input trace, to keep out unwanted interference signals from power lines, nearby power supplies, human bodies, etc.   -Bruce H. 

  • Hi Bruce,

    Thanks for your elaborative answer, it is helpful. I have understood the Guard and Shield requirements for this kind of low current measurement PCB design. Now the question is about the four-layer PCB. Are both inner layers defined as Vsum or just the layer below the top layer? Also in the case of voltage traces, the return path is normally lying just below the trace. But how about in the current trace, because I can see the GND layer on the bottom, and the top GND layer is far from the current trace(Inum). 

  • 0
    •  Analog Employees 
    on Jun 11, 2021 5:46 PM in reply to Tikull

    Hello Tikull,

    Attached below, you will find the Gerber files for the factory eval board. This enables use of a Gerber viewer program to view the board design onscreen. 

     Are both inner layers defined as Vsum or just the layer below the top layer? Normally just the layer 2, below the input trace. 

    Also in the case of voltage traces, the return path is normally lying just below the trace. But how about in the current trace, because I can see the GND layer on the bottom, and the top GND layer is far from the current trace(Inum).   Good question, and good to see you're considering the return current!  For these applications, the layout is a lot different from an RF layout. Impedance is really high at the input node, and capacitance should be kept as low as possible. So for these reasons, it's OK to have the return trace rather far from the input trace. The high impedance makes shielding more important, but the shielding is relatively simple compared to RF boards and systems.   -Bruce H. 

    ADL5304-EVALZ_Gerbers.zip