ADF4155 frac-N PN Floor PLLsim vs Datasheet?

The ADF4155 data sheet shows normalized phase noise floor spec as --218 in frac-N mode and -223 in Int mode.

I ran PllSim for an ADF4155 frac-N design  and the side panel shows (under Chip -> Phase Detector -> PN Floor) that it used -223 for a frac-N design.

I downloaded the latest PLLSim and datsheet and no change.

Which is correct PN floor for frac-N 4155?

Mike Lavelle

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    •  Analog Employees 
    on Oct 14, 2021 2:55 PM in reply to miclevel

    Hi Mike,

    I can't send any modified PLL models as these will only work on our custom in-house/debug version of ADIsimPLL for internal use only - the PLL models are fixed otherwise.

    We weren't able to get this fix into the ADisimPLL v5.4 release, but we will have a new version out in the coming weeks which allows simulations with the ADF4401A translation loop. The ADF4155 model will be updated in this next version. Sorry for the delay.

    Regards,

    Alex

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