Phase consistency between two ADF4159/ADF4169 PLLs

If both PLLs are outputting one single freq in integer mode then yes this is possible to keep the output of both in phase after each frequency write and it is relatively straightforward. You would just need to make sure all PLLs are sharing the same reference, and that the write to take counters out of reset happens to all PLLs at the same moment, by ensuring the SPI LE signal is sync'd with the REF. See here:

https://ez.analog.com/rf/f/q-a/73695/why-am-i-unable-to-repeat-the-phase-alignment-between-rfin-and-refin-using-the-adf4106

However, when using the SDM for fractional N channels, this is not so straightforward. Due to the various delays introduced by the sigma delta modulator in frac mode, it is not possible to keep phase coherence between adjacent frequency steps let alone multiple PLLs. 
See here<https://www.analog.com/en/technical-articles/phase-alignment-and-control-on-the-adf4356-5356-devices.html#:~:text=Phase%20resync%20is%20defined%20as%2cis%20reprogrammed%20back%20to%20F1.> for more info on this idea of frac vs int mode phase differences.

As you have pointed out, we have the phase resync feature on some of our PLLs to get around this. But the ADF4159 does not have this features since it's primarily a sweeper/ramping PLL.

With that said, it's possible to use additional external circuitry on the output stage to measure the phase and at which point both the phase of one of the PLLs to be adjusted to bring it in line with the other using the phase adjust feature.

Regards,

Alex

If both PLLs are outputting one single freq in integer mode then yes this is possible to keep the output of both in phase after each frequency write and it is relatively straightforward. You would just need to make sure all PLLs are sharing the same reference, and that the write to take counters out of reset happens to all PLLs at the same moment, by ensuring the SPI LE signal is sync'd with the REF. See here:

https://ez.analog.com/rf/f/q-a/73695/why-am-i-unable-to-repeat-the-phase-alignment-between-rfin-and-refin-using-the-adf4106

However, when using the SDM for fractional N channels, this is not so straightforward. Due to the various delays introduced by the sigma delta modulator in frac mode, it is not possible to keep phase coherence between adjacent frequency steps let alone multiple PLLs. 
See here<https://www.analog.com/en/technical-articles/phase-alignment-and-control-on-the-adf4356-5356-devices.html#:~:text=Phase%20resync%20is%20defined%20as%2cis%20reprogrammed%20back%20to%20F1.> for more info on this idea of frac vs int mode phase differences.

As you have pointed out, we have the phase resync feature on some of our PLLs to get around this. But the ADF4159 does not have this features since it's primarily a sweeper/ramping PLL.

With that said, it's possible to use additional external circuitry on the output stage to measure the phase and at which point both the phase of one of the PLLs to be adjusted to bring it in line with the other using the phase adjust feature.

Regards,

Alex