Hello ADI team,
I am an ASIC/FPGA contractor. In the company I work for these days - ADF4371 is used.
The FPGA configures the PLL according to commands from a host.
We see differences in output levels - with no reason found.
The device used is of rev. 0x09.
Things to note:
The bit var_mod_en definition in the version 0 data-sheet is opposite to the definition in version A data-sheet.
In the above screen-shot - var_mod_en is according to REV-A data-sheet.
In the following screen-shots - var_mod_en is constant 1. We hoped it will solve the 8.000 GHz problem, but it did not.
But we see power-level degradations in other frequencies.
and another one
Register-values that are not frequency-dependent - are set by the FPGA according to the registers-map of the ACE software.