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ADF4371 output-power varies

Itsik

Hello ADI team,

I am an ASIC/FPGA contractor. In the company I work for these days - ADF4371 is used.

The FPGA configures the PLL according to commands from a host.

We see differences in output levels - with no reason found.

The device used is of rev. 0x09.

Things to note:

The bit var_mod_en definition in the version 0 data-sheet is opposite to the definition in version A data-sheet.

In the above screen-shot - var_mod_en is according to REV-A data-sheet.

In the following screen-shots - var_mod_en is constant 1. We hoped it will solve the 8.000 GHz problem, but it did not.

But we see power-level degradations in other frequencies.

and another one

Register-values that are not frequency-dependent - are set by the FPGA according to the registers-map of the ACE software.

Please advise

Itsik

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  • 0
    •  Analog Employees 
    on May 5, 2021 8:12 AM

    Hi Itsik,

    Can you share your schematic (at least output section of it) and register values that you are using? 

    Kudret

  • 0 on May 5, 2021 2:50 PM in reply to kudret.unal

    PDF

    Fullscreen F9_reg_setting.txt Download 
    
    
       case param_raw_counter_int is
       
                when           0 =>  addr_to_spi <= X"0000";  
                                     data_to_spi <= X"00"; -- This means 3-wire SPI

                when           1 =>  addr_to_spi <= X"0001";  
                                     data_to_spi <= X"00";

                when           2 =>  addr_to_spi <= X"0003";  
                                     data_to_spi <= X"00";

                when           3 =>  addr_to_spi <= X"0004";  
                                     data_to_spi <= X"00";

                when           4 =>  addr_to_spi <= X"0005";  
                                     data_to_spi <= X"00";

                when           5 =>  addr_to_spi <= X"0006";  
                                     data_to_spi <= X"00";

                when           6 =>  addr_to_spi <= X"000C";  
                                     data_to_spi <= X"00";

                when           7 =>  addr_to_spi <= X"000D";  
                                     data_to_spi <= X"00";

                when           8 =>  addr_to_spi <= X"0010";  
                                     data_to_spi <= reg0010_data ; -- X"28" for 8 GHz

                when           9 =>  addr_to_spi <= X"0011";  
									 data_to_spi <= reg0011_data ; -- X"00" for 8 GHz

                when          10 =>  addr_to_spi <= X"0012";  
                                     data_to_spi <= X"40";

                when          11 =>  addr_to_spi <= X"0014";  
                                     data_to_spi <= reg0014_data ; -- X"00" for 8 GHz

                when          12 =>  addr_to_spi <= X"0015";  
                                     data_to_spi <= reg0015_data ; -- X"00" for 8 GHz

                when          13 =>  addr_to_spi <= X"0016"; 
                                     data_to_spi <= reg0016_data ; -- X"00" for 8 GHz

                when          14 =>  addr_to_spi <= X"0017";  
                                     data_to_spi <= reg0017_data ; -- X"00" for 8 GHz

                when          15 =>  addr_to_spi <= X"0018";  
                                     data_to_spi <= reg0018_data ; -- X"00" for 8 GHz

                when          16 =>  addr_to_spi <= X"0019";  
                                     data_to_spi <= reg0019_data ; -- X"01" for 8 GHz

                when          17 =>  addr_to_spi <= X"001A";  
                                     data_to_spi <= reg001A_data ; -- X"00" for 8 GHz

                when          18 =>  addr_to_spi <= X"001B";  
                                     data_to_spi <= X"00";

                when          19 =>  addr_to_spi <= X"001C";  
                                     data_to_spi <= X"00";

                when          20 =>  addr_to_spi <= X"001D";  
                                     data_to_spi <= X"00";

                when          21 =>  addr_to_spi <= X"001E";  
                                     data_to_spi <= X"48";

                when          22 =>  addr_to_spi <= X"001F";  
                                     data_to_spi <= reg001F_data ; -- X"01" for 8 GHz

                when          23 =>  addr_to_spi <= X"0020";  
                                     data_to_spi <= X"14";

                when          24 =>  addr_to_spi <= X"0021";  
                                     data_to_spi <= X"00";

                when          25 =>  addr_to_spi <= X"0022";  
                                     -- data_to_spi <= X"10";   -- This value fits 250 MHz
                                     -- data_to_spi <= X"20";   -- -- This value fits the GHz range
                                     data_to_spi <= reg0022_data ; -- X"00" for 8GHz

                when          26 =>  addr_to_spi <= X"0023";  
                                     data_to_spi <= reg0023_data ; -- X"00" for 8 GHz

                when          27 =>  addr_to_spi <= X"0024";  
                                     --data_to_spi <= X"D0";   -- This value fits 250 MHz
                                     data_to_spi <= X"80";   -- -- This value fits the GHz range

                when          28 =>  addr_to_spi <= X"0025";  
                                     --data_to_spi <= X"07";
                                     data_to_spi <= reg0025_data ; -- X"0A" for 8 GHz -- RF_EN reg - various values. 

                when          29 =>  addr_to_spi <= X"0026";  
                                     data_to_spi <= reg0026_data ; -- This is BLEED_ICP -- X"28" for 8 GHz

                when          30 =>  addr_to_spi <= X"0027";  
                                     data_to_spi <= reg0027_data ; -- X"C5" for 8 GHz

                when          31 =>  addr_to_spi <= X"0028";  
                                     data_to_spi <= X"83";

                when          32 =>  addr_to_spi <= X"002A";  
                                     data_to_spi <= X"00";
                                     
                when          33 =>  addr_to_spi <= X"002B";  
                                     data_to_spi <= reg002B_data ; -- bit 0 is the bit sd_en_frac0 -- X"01" for 8 GHz

                when          34 =>  addr_to_spi <= X"002C";  
                                     data_to_spi <= X"24";

                when          35 =>  addr_to_spi <= X"002D";  
                                     data_to_spi <= reg002D_data ; -- X"09" for 8 GHz

                when          36 =>  addr_to_spi <= X"002E";  
                                     data_to_spi <= reg002E_data ; -- X"0A" for 8 GHz

                when          37 =>  addr_to_spi <= X"002F";  
                                     data_to_spi <= reg002F_data ; -- X"0A" for 8GHz

                when          38 =>  addr_to_spi <= X"0030";  
                                     --data_to_spi <= X"15";   
                                     data_to_spi <= X"2A";     

                when          39 =>  addr_to_spi <= X"0031";  
                                     data_to_spi <= X"02";

                when          40 =>  addr_to_spi <= X"0032";  
                                     data_to_spi <= X"04";

                when          41 =>  addr_to_spi <= X"0033";  
                                     data_to_spi <= X"24";      

                when          42 =>  addr_to_spi <= X"0034"; 
                                     data_to_spi <= X"8A";      

                when          43 =>  addr_to_spi <= X"0035";  
                                     data_to_spi <= X"FF";      

                when          44 =>  addr_to_spi <= X"0036";  
                                     data_to_spi <= X"30";

                when          45 =>  addr_to_spi <= X"0037";  
                                     data_to_spi <= X"00";

                when          46 =>  addr_to_spi <= X"0038";  
                                     data_to_spi <= X"00";

                when          47 =>  addr_to_spi <= X"0039";  
                                     data_to_spi <= X"07";

                when          48 =>  addr_to_spi <= X"003A";  
                                     data_to_spi <= X"55";

                when          49 =>  addr_to_spi <= X"003D";  
                                     data_to_spi <= X"00";

                when          50 =>  addr_to_spi <= X"003E";  
                                     data_to_spi <= X"0C";

                when          51 =>  addr_to_spi <= X"003F";  
                                     data_to_spi <= X"80";

                when          52 =>  addr_to_spi <= X"0040";  
                                     data_to_spi <= X"50";

                when          53 =>  addr_to_spi <= X"0041";  
                                     data_to_spi <= X"28";

                when          54 =>  addr_to_spi <= X"0042";  
                                     data_to_spi <= X"00";

                when          55 =>  addr_to_spi <= X"0043";  
                                     data_to_spi <= X"00";

                when          56 =>  addr_to_spi <= X"0044";  
                                     data_to_spi <= X"00";

                when          57 =>  addr_to_spi <= X"0045";  
                                     data_to_spi <= X"00";

                when          58 =>  addr_to_spi <= X"0046";  
                                     data_to_spi <= X"00";

                when          59 =>  addr_to_spi <= X"0047";  
                                     data_to_spi <= X"C0";

                when          60 =>  addr_to_spi <= X"0052";  
                                     data_to_spi <= X"F4";

                when          61 =>  addr_to_spi <= X"006C";  
                                     data_to_spi <= X"00";

                when          62 =>  addr_to_spi <= X"006E";  
                                     data_to_spi <= X"00";

                when          63 =>  addr_to_spi <= X"006F";  
                                     data_to_spi <= X"00";

                when          64 =>  addr_to_spi <= X"0070";  
                                     data_to_spi <= reg0070_data ; -- X"E3" for 8 GHz

                when          65 =>  addr_to_spi <= X"0071";  
                                     data_to_spi <= reg0071_data ; -- -- X"E3" for 8 GHz

                when          66 =>  addr_to_spi <= X"0072";  
                                     data_to_spi <= X"32";

                when          67 =>  addr_to_spi <= X"0073";  
                                     data_to_spi <= X"00";

                when          68 =>  addr_to_spi <= X"0079";  
                                     data_to_spi <= X"00";

                when          69 =>  addr_to_spi <= X"007A";  
                                     data_to_spi <= X"00";

                when          70 =>  addr_to_spi <= X"007B";  
                                     data_to_spi <= X"00";

                when          71 =>  addr_to_spi <= X"007C";  
                                     data_to_spi <= X"00";
    
            when others =>
                                    addr_to_spi <= ( others => '0' ) ;  
                                    data_to_spi <= ( others => '0' ) ;
                                    assert ( false )
                                    report "File: F9_CONTROL: reached the 'OTHERS' entry in a case -line 1646"
                                    severity failure ; 
            
       end case ;

    Hello Kudret,

    Attached is the schematic of the board - the PLL that we are facing problems with.

    There are several ADF4371 and ADF4372 devices on the board. Board schematics is almost the same - depends on output frequency used.

    Most of the PLLs are configured to a fixed setting - we use the register setting from the ACE software - with the modifications of board-voltage-dependent registers. They work Fine.

    For the F9 PLL - our on-board FPGA configures the F9 PLL according to frequency setting from a host.

    The attached .txt file contains part of the VHDL file that configures this PLL.

    This part is a case block - that chooses address and data to the PLL according to the index.

    For most registers - the content written is fixed, fore some - our block generates the required values.

    The index param_raw_counter_int starts at 71 and decreases to 0. Thus reg0010  is written after all required registers

    have already been written.

    The same mechanism is used for all other PLL devices.

    Regards,

    Itsik

Reply
  • 0 on May 5, 2021 2:50 PM in reply to kudret.unal

    PDF

    Fullscreen F9_reg_setting.txt Download 
    
    
       case param_raw_counter_int is
       
                when           0 =>  addr_to_spi <= X"0000";  
                                     data_to_spi <= X"00"; -- This means 3-wire SPI

                when           1 =>  addr_to_spi <= X"0001";  
                                     data_to_spi <= X"00";

                when           2 =>  addr_to_spi <= X"0003";  
                                     data_to_spi <= X"00";

                when           3 =>  addr_to_spi <= X"0004";  
                                     data_to_spi <= X"00";

                when           4 =>  addr_to_spi <= X"0005";  
                                     data_to_spi <= X"00";

                when           5 =>  addr_to_spi <= X"0006";  
                                     data_to_spi <= X"00";

                when           6 =>  addr_to_spi <= X"000C";  
                                     data_to_spi <= X"00";

                when           7 =>  addr_to_spi <= X"000D";  
                                     data_to_spi <= X"00";

                when           8 =>  addr_to_spi <= X"0010";  
                                     data_to_spi <= reg0010_data ; -- X"28" for 8 GHz

                when           9 =>  addr_to_spi <= X"0011";  
									 data_to_spi <= reg0011_data ; -- X"00" for 8 GHz

                when          10 =>  addr_to_spi <= X"0012";  
                                     data_to_spi <= X"40";

                when          11 =>  addr_to_spi <= X"0014";  
                                     data_to_spi <= reg0014_data ; -- X"00" for 8 GHz

                when          12 =>  addr_to_spi <= X"0015";  
                                     data_to_spi <= reg0015_data ; -- X"00" for 8 GHz

                when          13 =>  addr_to_spi <= X"0016"; 
                                     data_to_spi <= reg0016_data ; -- X"00" for 8 GHz

                when          14 =>  addr_to_spi <= X"0017";  
                                     data_to_spi <= reg0017_data ; -- X"00" for 8 GHz

                when          15 =>  addr_to_spi <= X"0018";  
                                     data_to_spi <= reg0018_data ; -- X"00" for 8 GHz

                when          16 =>  addr_to_spi <= X"0019";  
                                     data_to_spi <= reg0019_data ; -- X"01" for 8 GHz

                when          17 =>  addr_to_spi <= X"001A";  
                                     data_to_spi <= reg001A_data ; -- X"00" for 8 GHz

                when          18 =>  addr_to_spi <= X"001B";  
                                     data_to_spi <= X"00";

                when          19 =>  addr_to_spi <= X"001C";  
                                     data_to_spi <= X"00";

                when          20 =>  addr_to_spi <= X"001D";  
                                     data_to_spi <= X"00";

                when          21 =>  addr_to_spi <= X"001E";  
                                     data_to_spi <= X"48";

                when          22 =>  addr_to_spi <= X"001F";  
                                     data_to_spi <= reg001F_data ; -- X"01" for 8 GHz

                when          23 =>  addr_to_spi <= X"0020";  
                                     data_to_spi <= X"14";

                when          24 =>  addr_to_spi <= X"0021";  
                                     data_to_spi <= X"00";

                when          25 =>  addr_to_spi <= X"0022";  
                                     -- data_to_spi <= X"10";   -- This value fits 250 MHz
                                     -- data_to_spi <= X"20";   -- -- This value fits the GHz range
                                     data_to_spi <= reg0022_data ; -- X"00" for 8GHz

                when          26 =>  addr_to_spi <= X"0023";  
                                     data_to_spi <= reg0023_data ; -- X"00" for 8 GHz

                when          27 =>  addr_to_spi <= X"0024";  
                                     --data_to_spi <= X"D0";   -- This value fits 250 MHz
                                     data_to_spi <= X"80";   -- -- This value fits the GHz range

                when          28 =>  addr_to_spi <= X"0025";  
                                     --data_to_spi <= X"07";
                                     data_to_spi <= reg0025_data ; -- X"0A" for 8 GHz -- RF_EN reg - various values. 

                when          29 =>  addr_to_spi <= X"0026";  
                                     data_to_spi <= reg0026_data ; -- This is BLEED_ICP -- X"28" for 8 GHz

                when          30 =>  addr_to_spi <= X"0027";  
                                     data_to_spi <= reg0027_data ; -- X"C5" for 8 GHz

                when          31 =>  addr_to_spi <= X"0028";  
                                     data_to_spi <= X"83";

                when          32 =>  addr_to_spi <= X"002A";  
                                     data_to_spi <= X"00";
                                     
                when          33 =>  addr_to_spi <= X"002B";  
                                     data_to_spi <= reg002B_data ; -- bit 0 is the bit sd_en_frac0 -- X"01" for 8 GHz

                when          34 =>  addr_to_spi <= X"002C";  
                                     data_to_spi <= X"24";

                when          35 =>  addr_to_spi <= X"002D";  
                                     data_to_spi <= reg002D_data ; -- X"09" for 8 GHz

                when          36 =>  addr_to_spi <= X"002E";  
                                     data_to_spi <= reg002E_data ; -- X"0A" for 8 GHz

                when          37 =>  addr_to_spi <= X"002F";  
                                     data_to_spi <= reg002F_data ; -- X"0A" for 8GHz

                when          38 =>  addr_to_spi <= X"0030";  
                                     --data_to_spi <= X"15";   
                                     data_to_spi <= X"2A";     

                when          39 =>  addr_to_spi <= X"0031";  
                                     data_to_spi <= X"02";

                when          40 =>  addr_to_spi <= X"0032";  
                                     data_to_spi <= X"04";

                when          41 =>  addr_to_spi <= X"0033";  
                                     data_to_spi <= X"24";      

                when          42 =>  addr_to_spi <= X"0034"; 
                                     data_to_spi <= X"8A";      

                when          43 =>  addr_to_spi <= X"0035";  
                                     data_to_spi <= X"FF";      

                when          44 =>  addr_to_spi <= X"0036";  
                                     data_to_spi <= X"30";

                when          45 =>  addr_to_spi <= X"0037";  
                                     data_to_spi <= X"00";

                when          46 =>  addr_to_spi <= X"0038";  
                                     data_to_spi <= X"00";

                when          47 =>  addr_to_spi <= X"0039";  
                                     data_to_spi <= X"07";

                when          48 =>  addr_to_spi <= X"003A";  
                                     data_to_spi <= X"55";

                when          49 =>  addr_to_spi <= X"003D";  
                                     data_to_spi <= X"00";

                when          50 =>  addr_to_spi <= X"003E";  
                                     data_to_spi <= X"0C";

                when          51 =>  addr_to_spi <= X"003F";  
                                     data_to_spi <= X"80";

                when          52 =>  addr_to_spi <= X"0040";  
                                     data_to_spi <= X"50";

                when          53 =>  addr_to_spi <= X"0041";  
                                     data_to_spi <= X"28";

                when          54 =>  addr_to_spi <= X"0042";  
                                     data_to_spi <= X"00";

                when          55 =>  addr_to_spi <= X"0043";  
                                     data_to_spi <= X"00";

                when          56 =>  addr_to_spi <= X"0044";  
                                     data_to_spi <= X"00";

                when          57 =>  addr_to_spi <= X"0045";  
                                     data_to_spi <= X"00";

                when          58 =>  addr_to_spi <= X"0046";  
                                     data_to_spi <= X"00";

                when          59 =>  addr_to_spi <= X"0047";  
                                     data_to_spi <= X"C0";

                when          60 =>  addr_to_spi <= X"0052";  
                                     data_to_spi <= X"F4";

                when          61 =>  addr_to_spi <= X"006C";  
                                     data_to_spi <= X"00";

                when          62 =>  addr_to_spi <= X"006E";  
                                     data_to_spi <= X"00";

                when          63 =>  addr_to_spi <= X"006F";  
                                     data_to_spi <= X"00";

                when          64 =>  addr_to_spi <= X"0070";  
                                     data_to_spi <= reg0070_data ; -- X"E3" for 8 GHz

                when          65 =>  addr_to_spi <= X"0071";  
                                     data_to_spi <= reg0071_data ; -- -- X"E3" for 8 GHz

                when          66 =>  addr_to_spi <= X"0072";  
                                     data_to_spi <= X"32";

                when          67 =>  addr_to_spi <= X"0073";  
                                     data_to_spi <= X"00";

                when          68 =>  addr_to_spi <= X"0079";  
                                     data_to_spi <= X"00";

                when          69 =>  addr_to_spi <= X"007A";  
                                     data_to_spi <= X"00";

                when          70 =>  addr_to_spi <= X"007B";  
                                     data_to_spi <= X"00";

                when          71 =>  addr_to_spi <= X"007C";  
                                     data_to_spi <= X"00";
    
            when others =>
                                    addr_to_spi <= ( others => '0' ) ;  
                                    data_to_spi <= ( others => '0' ) ;
                                    assert ( false )
                                    report "File: F9_CONTROL: reached the 'OTHERS' entry in a case -line 1646"
                                    severity failure ; 
            
       end case ;

    Hello Kudret,

    Attached is the schematic of the board - the PLL that we are facing problems with.

    There are several ADF4371 and ADF4372 devices on the board. Board schematics is almost the same - depends on output frequency used.

    Most of the PLLs are configured to a fixed setting - we use the register setting from the ACE software - with the modifications of board-voltage-dependent registers. They work Fine.

    For the F9 PLL - our on-board FPGA configures the F9 PLL according to frequency setting from a host.

    The attached .txt file contains part of the VHDL file that configures this PLL.

    This part is a case block - that chooses address and data to the PLL according to the index.

    For most registers - the content written is fixed, fore some - our block generates the required values.

    The index param_raw_counter_int starts at 71 and decreases to 0. Thus reg0010  is written after all required registers

    have already been written.

    The same mechanism is used for all other PLL devices.

    Regards,

    Itsik

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