ADF5901 RF output not stable

Hi,

We have developed a 24 GHz custom radar board with the ADF4159-ADF5901-ADF5904 setup. We program the Tx to generate 24Ghz and divide it by 4 to send it to PLL feedback in RF synthesis mode (no ramp). Once the initialization is done for both Tx and PLL chip for the required settings, we obtain a PLL lock Muxout of AD4159. But when I observe the Vtune output of PLL, it is not stable. It is fluctuating as shown in the picture around 1.8V. The feedback of the Tx is also fluctuating quickly like shown in picture around 6 Ghz. I am not able to check the output of Tx because I dont have access to 24Ghz spectrum analyzer at the moment. I cross checked the programming sequence by comparing it with the ADI-RADAR tool. 

Programming seq:

# Init adf5901 to gen 24ghz
x02000007
x0000002B
x0000000B
x1D32A64A
x2A20B929
x40003E88
x809FE520
x011F4827
x00000006
x01E00005
x00200004
x01890803
x00020642
xFFF7FFE1
x808FE720
# wait 800us
x808FE560
x808FED60
# wait 400us
x808FE5A0
x808FF5A0
# wait 400us
x2800B929
x808F25A0

# Init ADF4159 to gen Vtune for 6Ghz

x00000007
x00001f46
x00800006
x00380835
x00800005
x00781904
x00780144
x00420443
x00608052
x00000001
x303C0000

Could someone help me if I am doing anything wrong here? I tried with different charge pump current settings, when I used the least charge pump current, the Vtune was slightly smoother. We have designed the loop filter similar to the EV-RADAR-MMIC2 eval board.

Thanks

Top Replies

  • May 3, 2021 in reply to gensysco +1 verified

    Hi ggall

    We found the problem, it was related to the loop filter design. We used the tool provided by ADI to design the loop filter correctly and replaced the components on board. Since then, we have stable…

Parents
  • 0
    •  Analog Employees 
    on Apr 19, 2021 1:06 AM

    Assuming REFIN = 100 MHz, step 10 of the ADF5901 init sequence should be 0x01E28005 to centre the VCO frequency calibration at 24.125 GHz (N = 241.25). It looks like you are setting N = 240, which would centre the VCO calibration at 24 GHz, which is the minimum output frequency.

  • Hi

    Yes REFIN is 100Mhz. And yes I am trying to initialize the VCO to 24 Ghz. Our FMCW radar is designed to ramp from 24 to 24.25 Ghz. So I was trying to generate 24 Ghz output at initialization, and then configure it to ramp for 250 Mhz. 

    Are you saying that I cannot initialize the chip to 24 Ghz?

    Thanks

  • Hi 

    I have recalibrated the VCO to 24.125 GHz like you said. But still I see the Vtune of PLL is fluctuating like the in the previous picture. I am using the least charge pump setting for which I get the least fluctuation. As I use higher charge pump, the fluctuation becomes stronger. 

    I then tried the continous sawtooth ramping on PLL. For 250Mhz ramp on VCO, I configure the PLL to ramp for 62.5Mhz starting from 6Ghz. The Vtune looks like its ramping correctly, but the fluctuation itself is still visible. See picture below, the ramp is noisy. Do you think it is a configuration problem, or the loop filter? We have used the same loop filter as the eval board ev-radar-mmic2.

    Below is the new seq of register writes I am using,

    // init adf5901 to 24.125 Ghz
    x02000007
    x0000002B
    x0000000B
    x1D32A64A
    x2A20B929
    x40003E88
    x808FE520
    x011F4027
    x00000006
    x00f14005
    x00200004
    x01890803
    x00020642
    xFFF7FFE1
    x808FE720
    # wait 800us
    x808FE560
    x808FED60
    # wait 400us
    x808FE5A0
    x808FF5A0
    # wait 400us
    x2800B929
    x808F25A0

    // init pll to 6Ghz
    x00000007
    x00001f46
    x00800006
    x00380835
    x00800005
    x00781904
    x00780144
    x00820443
    x00408052
    x00000009
    x301E0000


    // configure pll ramp 100ms, 62.5Mhz, 25Khz steps
    x00000007
    x00004e1e
    x00084195
    x0078c804
    x00820043
    x00408052
    x00000009
    x781e0000
    xf81e0000

    I am not able to upload any images in the replies, so I have uploaded images of vtune ramp and also the settings I use in the eval_radar_mmic GUI to generate the above register sequence on this google drive.

    drive.google.com/.../1z0RGzJDiHRZXb-M4rlTYKR5B-BBI8FWq

    Thanks for your help!

  • 0
    •  Analog Employees 
    on Apr 26, 2021 8:40 AM in reply to gensysco

    I am not that familiar with the ADF4159, so I am tagging  who is the applications engineer for both parts.

    I am curious though why you are using the ADF5901 AUX outputs in VCO/4 mode (6 GHz) in your application, as the ADF4159 is configured to use the AUX outputs in VCO/2 mode (12 GHz) by default in the evaluation software. Have you tried using the default settings and do you see the same issue? See EV-RADAR-MMIC2 User Guide.

  • Hi

    There is no specific reason for me to try 6Ghz. I tried out the 12Ghz like you suggested but the response is the same. The vtune fluctuates and output frequency is not stable. And muxout indicates pll lock.

    Thanks

  • Hi

    We found the problem, it was related to the loop filter design. We used the tool provided by ADI to design the loop filter correctly and replaced the components on board. Since then, we have stable vtune after locking and also while ramping.

    Thanks for your support.

  • 0
    •  Analog Employees 
    on May 4, 2021 7:33 AM in reply to gensysco

    Thanks for the update - glad you were able to resolve the issue.

    Yes, please use our free tool ADIsimPLL to design loop filters for our products.

Reply Children
No Data