Hello! I'm using the adf4002 as an int-N PLL with reference frequency = 10MHz and desired output frequency = 80MHz (The specified VCO is CVCO55CL-0060-0110). I think i have set the right value to the corresponding register. The PD polarity bit in initialization latch was set to 0 and 1 seperately to test while the output are both unlocked, jumping from 30MHz to 90MHz. And i have tested one group of Vtune as showned below. Any ideas on solving the problem? Thanks for your help!