AD9865 RX/TX nibbles

Hi,

The AD9865 datasheet states that "For the AD9865, the most significant nibble defaults to 6 bits, and the least significant nibble defaults to 4 bits". However, I can't find whether the 4-bit nibble (i.e., when RXSYNC is low) is RXD[5:2] or RXD[3:0].

From the 5/5 nibble mode, I can guess that only the higher bits of of RXD are used but would you please confirm this? Is this also the same for the TXD port?

Thank you!

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  • +1
    •  Analog Employees 
    on Mar 9, 2021 3:50 PM in reply to reza_ameli

    In this case, you will operate with a 6-bit bus where the most significant nibble appearing with RXSYNC is low (default) and the 4-least significant bits appearing (left justified) when RXSYNC is high.   The two LSB's during this phase (appearing at RX0 and RX1 pins) should remain static can can be ignored (truncated) when doing post processing on the 10-bit Rx Data.

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