1) What is the cause of the line slope of the Frequency Error in figures ADF4159_3.bmp and ADF4159_4.bmp?

2) How can this slope be eliminated and a constant average frequency error level can be maintained over the entire ramp duration (see ADIsimPLL configuration settings in figures ADF4159_1,2,3,4)?

3) Why is the "Design Freq" value in figure ADF4159_1.bmp written in red?







  • +1
    •  Analog Employees 
    on Feb 26, 2021 2:44 PM 1 month ago


    1) This is caused by the overshoot at the end of a ramp, since there is a large frequency jump made at the end of a ramp(moving from final ramp frequency back to first)

    2) The loop filter can be modified to reduce overshoot at the cost of reduced ramp linearity. You are using quite a wide LBW hence the large overshoot. Reducing the LBW will reduce overshoot slightly at the cost of a less linear ramp. Also, increasing the phase margin of the loop filter will also reduce the overshoot.  But it will cause some non-linearity at the start of the next ramp. So it is all a trade-off

    3) Not sure what the red text means. Do you want to attached your ADIsimPLL file here and I will see what it could be?

  • Hi,

    Thank you for your reply.
    I am a colleague of Vladimir, he still has a problem with authorization.
    We meant the slope of the line highlighted in purple. How can this parasitic slope (which determines the degree of nonlinearity of the frequency modulation law) depends on a later event at the end of the ramp?
    The Design110_110.pll file is located here :

  • 0
    •  Analog Employees 
    on Mar 2, 2021 5:02 PM 1 month ago in reply to Andrew Lu


    I see what Vladimir is taking about now. I misunderstood before, I thought the question was how to minimize the large overshoots.

    For more information please open ADIsimPLL then go to Help>Help Topics and search for Ramp Analysis topic. 

    I do not think it is possible to flatten out the frequency error completely across the ramp duration since the amount of frequency error is tied into the exact vtune/kVCO setting of the VCO, and ADIsimPLL will simulate this when it runs the chirp analysis. So I think this is expected, and the only thing that can be minimised is the RMS variations by changing the LBW, as detailed in the help guide mentioned above.

    I think the red highlighted text is a display glitch in the software, I do not think it corresponds to an actual error.



  • Hi,

    In this context, how to understand the K mismatch in the PLL configuration dialog and in the report (448 and 412.5 MHz / V, respectively)? Is this the reason for our problem?

  • 0
    •  Analog Employees 
    on Mar 4, 2021 11:30 AM 1 month ago in reply to Andrew Lu

    Since the VCO tuning curve is not a perfectly straight line, the exact kVCO will vary slightly over frequency.

    The kVCO from the VCO selection table is just an average kVCO to give a rough idea of tuning. I guess it's the kVCO at the center frequency. 

    The kVCO in the report is the exact value for the locked frequency, since at that point you have given it which frequency it will operating at and so it can give a more accurate estimate.

    Basically, kVCO variations over frequency are completely expected and okay. Most VCOs do not have a perfectly linear tuning curve