SPI Write to ADAR1000

All write modes are listed in the datasheet.  If the address was non-consecutive, then the part would not know which address to write the 2nd data byte to.  It seems like the only way to achieve this is to have that 2nd register's address already loaded into another register and have an enable bit asserted for this sort of non-consecutive write mode. 

I actually have another question regarding block write mode. If I have a 4 ADAR1000's in a CSB group, will the address of the chips increment as well? Or do I need to rewrite for each chip in the group?

Are you asking if you want to use Block Write mode AND Write All mode, such that all 4 chips get the same several registers of data contained in the single Block Write?  If so, I think this should work. 

No, sorry if my question is unclear. I have an array of ADAR1000's that I am trying to control. I want each chip that share a CSB to have different phase and gain values. So I'm curious as to how I should write to them. Would I just use a block write for each individual chip as they have different addresses? I.e. use a different SPI address at the beginning to denote each separate chip (00 -> 01 -> 10 -> 11).  

You can use the chip address pins (ADDR1 and ADDR0) to set each chips hardware address, and then access each chip individually with their hardware address via the SPI address bits [14:13].  See the chip addresses section on page 27 of the Revision A datasheet.

And then just block write the gain and phase data to each chip.

You can use the chip address pins (ADDR1 and ADDR0) to set each chips hardware address, and then access each chip individually with their hardware address via the SPI address bits [14:13].  See the chip addresses section on page 27 of the Revision A datasheet.

And then just block write the gain and phase data to each chip.

Got it, thanks! I am still a bit confused on the block write mode though. When looking at the example program in table 20 not all the address are consecutive. Why is it that after the first write to 0x00, the next address being written to is 0x401 and then 0x400? 

Table 20 is not an example of a SPI block write, but rather individual SPI writes.

Huh, doesn't this directly conflict with my first question regarding other write modes since this is is a direct SPI write where the first byte is address and the second byte is data? Neither a block write or write all.

And if table 20 isn't a block write program then why does the first line "Reset whole chip, use SDO line for readback, address auto incrementing in block write mode" ? 

Perhaps I misunderstood your original question.

The individual register SPI write is the standard SPI write.  There is always 16 address bits, followed by 8 data bits clocked in, while the CSB is low.  You can perform this SPI transaction as many times as you need to.

I thought you originally wanted to know if you could write the following in a block write style:

[address1, data1, data2]

but data2 would not be written to the next consecutive address, but some other arbitrary address.

As far as table 20 goes, just because you setup address auto incremented (aka address ascension), does not mean you will actually perform a block write (that uses the address ascension).  You can always perform a Block Write, regard of the address ascension setting.  You can have either address ascension or descension in block write mode, i.e. next address data is written to is either n + 1 or n -1, respectively.  This is controlled with Bits 2 and 5 in Register 0x00; 0 = descension, 1 = ascension.   

Hope this clears up the confusion.

Ahh okay, that helps a lot. 

From what I can understand, and please correct me if I'm wrong. I can always write the 16 bit address followed by an 8 bit data value, and this can be repeated indefinitely provided I always give the new 16bit address before the 8 bit data value. If I want to block write, I would leave out the address, but the data must be for the register immediately after the initial address.